The gate bias and geometry dependence of random telegraph signal amplitudes [MOSFET]

Martin, S. T.; Li, G.P.; Worley, E.; White, J.

doi:10.1109/55.622524

Cited by 32 publications

(33 citation statements)

References 11 publications

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“…Trapping of a single carrier charge in defect states near the Si/SiO interface, and the related local modulation in carrier density and/or mobility [68]- [70] in an area comparable with the characteristic device dimensions, will have a profound effect on the drain and gate current [71] in decananometer MOSFETs. Corresponding random telegraph signals (RTS) with amplitudes larger than 60% have already been reported at room temperature in decananometer channel width devices [72].…”

Section: B Single Charge Trappingmentioning

confidence: 99%

Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs

Asenov

Brown

Davies

et al. 2003

IEEE Trans. Electron Devices

504

251

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Abstract-Intrinsic parameter fluctuations introduced by discreteness of charge and matter will play an increasingly important role when semiconductor devices are scaled to decananometer and nanometer dimensions in next-generation integrated circuits and systems. In this paper, we review the analytical and the numerical simulation techniques used to study and predict such intrinsic parameters fluctuations. We consider random discrete dopants, trapped charges, atomic-scale interface roughness, and line edge roughness as sources of intrinsic parameter fluctuations. The presented theoretical approach based on Green's functions is restricted to the case of random discrete charges. The numerical simulation approaches based on the drift diffusion approximation with density gradient quantum corrections covers all of the listed sources of fluctuations. The results show that the intrinsic fluctuations in conventional MOSFETs, and later in double gate architectures, will reach levels that will affect the yield and the functionality of the next generation analog and digital circuits unless appropriate changes to the design are made. The future challenges that have to be addressed in order to improve the accuracy and the predictive power of the intrinsic fluctuation simulations are also discussed.

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Section: B Single Charge Trappingmentioning

confidence: 99%

Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs

Asenov

Brown

Davies

et al. 2003

IEEE Trans. Electron Devices

504

251

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“…In next generation MOSFETs with sub 100 nm (decanano) dimensions [1], current fluctuations, caused by trapping of single carriers at the Si/SiO 2 interface, and related local modulation in carrier density and/or mobility [2,3], are becoming increasingly important. Corresponding random telegraph signals (RTS) with amplitudes larger than 60% have been reported already at room temperature in very narrow channel devices [4].…”

Section: Introductionmentioning

confidence: 99%

“…Corresponding random telegraph signals (RTS) with amplitudes larger than 60% have been reported already at room temperature in very narrow channel devices [4]. Current fluctuations on such a scale will become a serious issue, not only in analogue circuits, but also in mixed-mode [3] and digital applications. Although the RTS in MOSFETs have been studied experimentally for a relatively long period of time, the developed analytical models [5] and simplified numerical simulation studies [6] can not explain the wide range of RTS amplitudes observed in otherwise identical devices [7].…”

Section: Introductionmentioning

confidence: 99%

Random telegraph signal amplitudes in sub 100 nm (decanano) MOSFETs: a 3D 'Atomistic' simulation study

Asenov

Balasubramaniam

Brown

et al.

International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)

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In this paper we use 3D simulations to study the amplitudes of random telegraph signals (RTS) associated with the trapping of a single carrier in interface states in the channel of sub 100 nm (decanano) MOSFETs. Both simulations using continuous doping charge and random discrete dopants in the active region of the MOSFETs are presented. We have studied the dependence of the RTS amplitudes on the position of the trapped charge in the channel and on the device design parameters. We have observed a significant increase in the maximum RTS amplitude when discrete random dopants are employed in the simulations.

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“…Trapping of a single carrier charge in defect states near the Si/gate dielectric interface and the related local modulation in carrier density and/or mobility [2], [3] will have a profound effect on the drain and gate current in such devices [4]. Corresponding random telegraph signals (RTSs) with amplitudes as large as 60% have been already observed experimentally [5].…”

Section: Introductionmentioning

confidence: 99%

“…Such simulations only capture the electrostatic effects that create an inversion layer exclusion region around the trapped charge and reduces the overall current flowing through the device. It is still debatable in the literature as to what extents the electrostatic reduction in the carrier density or the increased scattering in the channel effects the current reduction in response to the charge trapping, thus determining the magnitude of the RTS amplitudes [2], [3], [13].…”

Section: Introductionmentioning

confidence: 99%

Impact of Single Charge Trapping in Nano-MOSFETs—Electrostatics Versus Transport Effects

Alexander

Brown

Watling

et al. 2005

IEEE Trans. Nanotechnology

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The gate bias and geometry dependence of random telegraph signal amplitudes [MOSFET]

Cited by 32 publications

References 11 publications

Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs

Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs

Random telegraph signal amplitudes in sub 100 nm (decanano) MOSFETs: a 3D 'Atomistic' simulation study

Impact of Single Charge Trapping in Nano-MOSFETs—Electrostatics Versus Transport Effects

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