The GBT-FPGA core: features and challenges

Marı́n, M.; Baron, S.; Feger, Sebastian S.; Leitao, Pedro; Lupu, EC; Soós, C.; Vichoudis, P.; Wyllie, K.

doi:10.1088/1748-0221/10/03/c03021

Cited by 64 publications

(53 citation statements)

References 11 publications

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“…The approach ensures frequency stability with low jitter of the recovered phase locked clock. If the links are operated in latency optimized mode [15] then the latency or the delay path of the data lines remains constant, and is needed for the Timing, Trigger and Control (TTC) data communication. While other levels of complex synchronous information handling like the time-stamp and the trigger management are preserved at the higher level of the CRU firmware logic stack.…”

Section: High-speed Serial Links In the Ttc Communicationmentioning

confidence: 99%

Trigger and timing distributions using the TTC-PON and GBT bridge connection in ALICE for the LHC Run 3 Upgrade

Mitra

David

Méndez

et al. 2019

Nuclear Instruments and Methods in Physics Research Section A:

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The ALICE experiment at CERN is preparing for a major upgrade for the third phase of data taking run (Run 3 ), when the high luminosity phase of the Large Hadron Collider (LHC) starts. The increase in the beam luminosity will result in high interaction rate causing the data acquisition rate to exceed 3 TB/sec. In order to acquire data for all the events and to handle the increased data rate, a transition in the readout electronics architecture from the triggered to the trigger-less acquisition mode is required. In this new architecture, a dedicated electronics block called the Common Readout Unit (CRU) is defined to act as a nodal communication point for detector data aggregation and as a distribution point for timing, trigger and control (TTC) information. TTC information in the upgraded triggerless readout architecture uses two asynchronous high-speed serial links connections: the TTC-PON and the GBT. We have carried out a study to evaluate the quality of the embedded timing signals forwarded by the CRU to the connected electronics using the TTC-PON and GBT bridge connection. We have used four performance metrics to characterize the communication bridge: (a) the latency added by the firmware logic, (b) the jitter cleaning effect of the PLL on the timing signal, (c) BER analysis for quantitative measurement of signal quality, and (d) the effect of optical transceivers parameter settings on the signal strength. Reliability study of the bridge connection in maintaining the phase consistency of timing signals is conducted by performing multiple iterations of power on/off cycle, firmware upgrade and reset assertion/de-assertion cycle (PFR cycle). The Intel development kit having Arria 10 FPGA is used for developing the first prototype of the CRU firmware. The test results are presented and discussed concerning the performance of the TTC-PON and GBT bridge communication chain using the CRU prototype and its compliance with the ALICE timing requirements.

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Section: High-speed Serial Links In the Ttc Communicationmentioning

confidence: 99%

Trigger and timing distributions using the TTC-PON and GBT bridge connection in ALICE for the LHC Run 3 Upgrade

Mitra

David

Méndez

et al. 2019

Nuclear Instruments and Methods in Physics Research Section A:

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“…1 features three different interfacing links: (i) the Data link, which connects the detector FEE to RU, (ii) the Trigger link, which connects the RU to the trigger system of the experiment, and (iii) the DAQ link, which takes the data from the RU to the storage and computing nodes. For the data link, the Gigabit Transceiver (GBT) protocol architecture [17], developed at CERN, has been found to be most ideal. The GBT protocol supports 4.8 Gb/sec data transmission rate.…”

Section: High-speed Protocolsmentioning

confidence: 99%

Optimization of multi-gigabit transceivers for high speed data communication links in HEP Experiments

Khan

Mitra

Das

et al. 2019

Nuclear Instruments and Methods in Physics Research Section A:

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The scheme of the data acquisition (DAQ) architecture in High Energy Physics (HEP) experiments consist of data transport from the front-end electronics (FEE) of the online detectors to the readout units (RU), which perform online processing of the data, and then to the data storage for offline analysis. With major upgrades of the Large Hadron Collider (LHC) experiments at CERN, the data transmission rates in the DAQ systems are expected to reach a few TB/sec within the next few years. These high rates are normally associated with the increase in the high-frequency losses, which lead to distortion in the detected signal and degradation of signal integrity. To address this, we have developed an optimization technique of the multi-gigabit transceiver (MGT) and implemented it on the state-of-the-art 20nm Arria-10 FPGA manufactured by Intel Inc. The setup has been validated for three available high-speed data transmission protocols, namely, GBT, TTC-PON and 10 Gbps Ethernet. The improvement in the signal integrity is gauged by two metrics, the Bit Error Rate (BER) and the Eye Diagram. It is observed that the technique improves the signal integrity and reduces BER. The test results and the improvements in the metrics of signal integrity for different link speeds are presented and discussed.

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“…And RJ45 Cat6 cables are used for connecting six IBL DC modules and the Telescope Readout FMC Card. There are two GBT links between the front end and the FELIX in the back end: one is used to distribute the clock signal for synchronization, and the other is for data transmission [8] [9]. The FE-I4B output data from the IBL modules are mapped to the 4-bit Elinks directly in the GBT frame.…”

Section: Readout System Overviewmentioning

confidence: 99%

Development of Telescope Readout System Based on FELIX for Testbeam Experiments

Wu¹,

Benoit²,

Liu³

et al. 2018

Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP-17)

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The High Voltage CMOS (HV-CMOS) sensors are extensively investigated by the ATLAS collaboration in the High-Luminosity LHC (HL-LHC) upgrade of the Inner Tracker (ITk) detector. A testbeam telescope, based on the ATLAS IBL (Insertable B-Layer) silicon pixel modules, has been built to characterize the HV-CMOS sensor prototypes. The Front-End LInk eXchange (FE-LIX) system is a new approach to function as the gateway between front-ends and the commodity switched network in the different detectors of the ATLAS upgrade. A FELIX based readout system has been developed for the readout of the testbeam telescope, which includes a Telescope Readout FMC Card as interface between the IBL DC (double-chip) modules and a Xilinx ZC706 evaluation board. The test results show that the FELIX based telescope readout system is capable of sensor calibration and readout of a high-density pixel detector in test beam experiments in an effective way.

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The GBT-FPGA core: features and challenges

Cited by 64 publications

References 11 publications

Trigger and timing distributions using the TTC-PON and GBT bridge connection in ALICE for the LHC Run 3 Upgrade

Trigger and timing distributions using the TTC-PON and GBT bridge connection in ALICE for the LHC Run 3 Upgrade

Optimization of multi-gigabit transceivers for high speed data communication links in HEP Experiments

Development of Telescope Readout System Based on FELIX for Testbeam Experiments

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