The Generalized Deadlock Resolution Problem

Jain, Kamal; Hajiaghayi, MohammadTaghi; Talwar, Kunal

doi:10.1007/11523468_69

Cited by 8 publications

(12 citation statements)

References 18 publications

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“…Knapp introduced the WFGs [40] to model concurrency constraints directly between tasks. As discussed earlier, variations of WFGs are used in the state-of-the-art on deadlock detection for distributed message passing and (static membership) barriers [34,37].…”

Section: Task-event Graphsmentioning

confidence: 99%

Dynamic Deadlock Verification for General Barrier Synchronisation

Cogumbreiro

Martins

et al. 2018

ACM Trans. Program. Lang. Syst.

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We present Armus, a verification tool for dynamically detecting or avoiding barrier deadlocks. The core design of Armus is based on phasers, a generalisation of barriers that supports split-phase synchronisation, dynamic membership, and optional-waits. This allows Armus to handle the key barrier synchronisation patterns found in modern languages and libraries. We implement Armus for X10 and Java, giving the first sound and complete barrier deadlock verification tools in these settings. Armus introduces a novel event-based graph model of barrier concurrency constraints that distinguishes task-event and event-task dependencies. Decoupling these two kinds of dependencies facilitates the verification of distributed barriers with dynamic membership, a challenging feature of X10. Further, our base graph representation can be dynamically switched between a task-to-task model, Wait-for Graph (WFG), and an event-to-event model, State Graph (SG), to improve the scalability of the analysis. Formally, we show that the verification is sound and complete with respect to the occurrence of deadlock in our core phaser language, and that switching graph representations preserves the soundness and completeness properties. These results are machine checked with the Coq proof assistant. Practically, we evaluate the runtime overhead of our implementations using three benchmark suites in local and distributed scenarios. Regarding deadlock detection, distributed scenarios show negligible overheads and local scenarios show overheads below 1.15×. Deadlock avoidance is more demanding, and highlights the potential gains from dynamic graph selection. In one benchmark scenario, the runtime overheads vary from 1.8× for dynamic selection, 2.6× for SG-static selection, and 5.9× for WFG-static selection.

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Section: Task-event Graphsmentioning

confidence: 99%

Dynamic Deadlock Verification for General Barrier Synchronisation

Cogumbreiro

Martins

et al. 2018

ACM Trans. Program. Lang. Syst.

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“…In concurrent software, various formal verification techniques are employed to exhaustively search for deadlock situations in concurrent protocols [10][11][12][13][14]. 1 In essence, synchronization protocols at a high level of abstraction, either extracted from the designs or defined a priori, are formally verified.…”

Section: Related Workmentioning

confidence: 99%

“…The second step contains two cases. First, if a cycle contains only single dependency vertices and ANDdependency vertices then it is a deadlock (lines 12-13); second, if a cycle contains a mixture including OR-dependency vertices, it is a deadlock if only all the outgoing branches of the OR-dependency vertices contains in some cycles (lines [14][15][16][17][18][19][20][21][22][23][24][25][26].…”

mentioning

confidence: 99%

Runtime deadlock analysis for system level design

Cheung

Chen²,

Hsieh

et al. 2009

Des Autom Embed Syst

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In the design of highly complex, heterogeneous and concurrent systems, deadlock detection remains an important issue. In this paper, we systematically analyze the synchronization dependencies in system-level designs. We propose a data structure called the dynamic synchronization dependency graph, which captures the runtime blocking dependencies among concurrent processes. A loop-detection algorithm is then used to detect deadlocks and help designers quickly isolate and identify modeling errors that cause the deadlock problems. We demonstrate our approach through two publicly available systemlevel modeling languages, SystemC and Metropolis, and two real world design examples, which are complex system-level functional models for video processing.

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“…Finding the largest size of an acyclic set in a digraph is equivalent to finding a set of vertices of minimum size which has a non-empty intersection with each directed cycle. In [8], Jain et al investigated the applications of this problem in deadlock resolution.…”

Section: Introductionmentioning

confidence: 99%

Acyclic Subgraphs of Planar Digraphs

Golowich¹,

Rolnick

2015

Electron. J. Combin.

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An acyclic set in a digraph is a set of vertices that induces an acyclic subgraph. In 2011, Harutyunyan conjectured that every planar digraph on n vertices without directed 2-cycles possesses an acyclic set of size at least 3n/5. We prove this conjecture for digraphs where every directed cycle has length at least 8. More generally, if g is the length of the shortest directed cycle, we show that there exists an acyclic set of size at least (1 − 3/g)n.

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The Generalized Deadlock Resolution Problem

Cited by 8 publications

References 18 publications

Dynamic Deadlock Verification for General Barrier Synchronisation

Dynamic Deadlock Verification for General Barrier Synchronisation

Runtime deadlock analysis for system level design

Acyclic Subgraphs of Planar Digraphs

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