The generation and characterization of electron and hole traps created by hole injection during low gate voltage hot-carrier stressing of n-MOS transistors

The Impact of Repetitive Unclamped Inductive Switching on the Electrical Parameters of Low-Voltage Trench Power nMOSFETs

“…If the hole current resulting from impact ionization is large enough, the MOSFET would undergo bipolar thermal runaway in a single pulse of UIS, hence the SOA on the MOSFET's datasheet would reflect the limitations of the device. The observation of hot-hole injection is in agreement with the work of Doyle et al [26,27] which showed that hole injection dominates the degradation mechanism at low gate voltages (V GS ) whereas electron injection dominates the degradation mechanism at high gate voltages. For power MOSFETs, this translates to hot-hole injection being the active degradation mechanism during avalanche operation (V GS =0 V and V DS =B VDSS ) and hot-electron degradation being the active degradation mechanism during linear mode operation (V GS and V DS = High).…”

“…The two types of defects generated by HCI are interface state defects and fixed oxide charge defects [26,27]. The electrical impact of increased interface trap generation due to repetitive avalanche would be an increase in the subthreshold slope as a result of increased interface trap capacitance [26].…”

“…6 shows the subthreshold slope as a function of N where it can be seen that the subthreshold slope is stable through out the UIS experiment. [26,27] which is also the point of maximum substrate current. These results, which are in agreement with [26,27], show that interface state generation is not an active degradation mechanism in avalanche mode operation.…”

Automated MOS Transistor Gamma Degradation Measurements Based on LabVIEW Environment

“…A major concern in the reliability of metal-oxide-semiconductor field effect transistor (MOSFET) devices is the formation of interface traps and near-interface oxide traps; called also border traps; under hot carrier injection, irradiation and processing. Traps at or near the semiconductor/gate dielectric interface can cause degraded transconductance (Doyle et al, 1990), the shifting of threshold voltage (Tsuchiya et al, 1987) and may lead to dielectric breakdown (Chen et al, 1985). In order to improve the resistance of MOSFET devices to these effects, it is necessary to have a reliable method of determining the densities of both interface traps and oxide traps (Djezzar et al, 2004).…”

Modeling of Surface Potential and Threshold Voltage of LDD nMOSFET′s with Localized Defects

“…This leads to an increase of the injection of the hot carriers in the oxide and at the interface. Therefore, localized defects near the drain are created [1][2][3]. These defects generate a parasitic currents *Corresponding author, e-mail: abouhdada@hotmail.com 62 A. BOUHDADA AND R. MARRAKH [4--6].…”