The High-Mobility Bended n-Channel Silicon Nanowire Transistor

Abstract

Abstract-This work demonstrates a method for incorporating strain in silicon nanowire gate-all-around (GAA) n-MOSFETs by oxidation-induced bending of the nanowire channel and reports on the resulting improvement in device performance. The variation in strain measured during processing is discussed. The strain profile in silicon nanowires is evaluated by Raman spectroscopy both before device gate stack fabrication (tensile strains of up to 2.5% are measured) and by measurement through the polysilicon gate on completed electrically characterized devices. Drain current boosting in bended n-channels is investigated as a function of the transistor operation regime, and it is shown that the enhancement depends on the effective electrical field. The maximum observed electron mobility enhancement is on the order of 100% for a gate bias near the threshold voltage. Measurements of stress through the full gate stack and experimental device characteristics of the same transistor reveal a stress of 600 MPa and corresponding improvements of the normalized drain current, normalized transconductance, and low-field mobility by 34% (at maximum gate overdrive), 50% (at g max ), and 53%, respectively, compared with a reference nonstrained device at room temperature. Finally, it is found that, at low temperatures, the low-field mobility is much higher in bended devices, compared with nonbended devices.

Top-down fabricated silicon nanowires under tensile elastic strain up to 4.5%

“…From a materials point of view our results are also unique as they demonstrate extremely high uniform strain along x, y and z orthogonal directions (see Fig. 2b) in contrast to those found in a NW bending geometry 21 . The strain levels are still lower than the theoretical tensile strength of a brittle material, which is expected to be ~E/10, where E is the Young`s modulus.…”

“…A feasible approach would be, for example, to employ the well-established gate-all-around architeture 10,21 . In order to realize this design, we propose employing a gate last process in order to avoid strain relaxation, where activation of source and drain is performed before patterning, and where low temperature conformal deposition of high-κ gate oxide and metal gate is achieved using atomic layer deposition 22 .…”

Mobility enhancement of strained Si transistors by transfer printing on plastic substrates

“…The suspended ribbons are anchored on both edges, and hence the biaxial tensile stress in the ribbons generally generates a boat shape because of (Figure 1b). 27,28 The extent and distribution of strain can be evaluated by analyzing the degree of buckling and the deformed shape. 29 Figure 1c presents the result of a three-dimensional height profile of the suspended Si/SiO 2 ribbon measured by white light interferometry.…”

Accumulation-mode gate-all-around si nanowire nMOSFETs with sub-5nm cross-section and high uniaxial tensile strain

“…To extract the low-field electron mobility, a cylindrical model, similar to [16], was used to expect the C ox value for the GAA deeply scaled nanowires. In this work, the extracted low-field electron mobility at V DS = 100 mV is 332 cm 2 /V s, 32% higher than bulk Si electron mobility at the same level of doping (1 Â 10 18 cm À3 ) [17], which is an evidence of including uniaxial tensile stress in the channel, and possibly a higher level can be achieved in this level of stress [7] in the case of an optimum dielectric-channel interface quality especially for the deeply scaled channels [18].…”