The HIPERLAN equalizer ASIC complexity and its relationship with the training header

Daneshrad, Babak

doi:10.1007/bf00461150

Cited by 6 publications

(3 citation statements)

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“…• A real multiply is assumed to be approximately eight times more complex than a real add [27]. • Shift operations are excluded from the calculations.…”

Section: E System Level Comparison Of the Two Algorithmsmentioning

confidence: 99%

A very low-complexity space-time block decoder (STBD) ASIC for wireless systems

Cavus

Daneshrad

2006

IEEE Trans. Circuits Syst. I

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This paper presents a computationally efficient application-specific integrated circuit (ASIC) implementation for the decoding of space-time block codes (STBCs) . Alternative methods of evaluating the originally proposed maximum-likelihood decision metrics are explored at the algorithm and architectural level. At the algorithm level, unique decoding techniques are developed that result in computation savings of as much as 65%. At the architectural level, a low-computation symmetrical approach for the implementation of the proposed algorithm is presented. The proposed ASIC architecture offers considerable computation reductions leading to substantial power and area savings compared to a direct implementation of the original algorithm. The proposed architecture was realized in an ASIC referred to as the ST block decoder ASIC. The chip was fabricated using 0.18-m CMOS technology and occupies a core area of 0.25 mm 2 . The ASIC architecture is highly scalable and can implement 2 2, 8 3, and 8 4 STBCs with modulation formats ranging from binary-phase shift keying (BPSK) to 16 quadrature amplitude modulation (QAM), and can operate at any symbol rate up to 20 Mbaud. Depending on the mode of operation, the decoder power consumption ranges from 0.54 mW for 2 2 BPSK systems to 1.89 mW for 8 4 16-QAM systems.Index Terms-Decoder application-specific integrated circuit (ASIC), low complexity, low power, space-time block codes (STBCs), transmit diversity, 3G.

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“…• A real multiply is assumed to be approximately eight times more complex than a real add [27]. • Shift operations are excluded from the calculations.…”

Section: E System Level Comparison Of the Two Algorithmsmentioning

confidence: 99%

A very low-complexity space-time block decoder (STBD) ASIC for wireless systems

Cavus

Daneshrad

2006

IEEE Trans. Circuits Syst. I

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“…Therefore the system must be designed to converge automati cally to a set of coefficient values which allow for relatively error free data reception. To accomplish this, many systems use what is called a training sequence [3], [14], [21], [22].…”

Section: Trainingmentioning

confidence: 99%

“…Unfortunately, the use of a training sequence requires the storage (or generation) of the sequence in both the transmitter and receiver [21]. This has two major consequences, the first is the obvious increase in size of the transceiver archi tectures and more importantly cost [22]. The second is the fact that both the transmitter and receiver must share this common sequence exactly.…”

Section: Trainingmentioning

confidence: 99%

Blind adaptation of a decision feedback equalizer for use in a 10Gbps serial link

Berndt¹

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The Decision Feedback Equalizer (DFE) is commonly used in recovering data at the receive end of a multi-gigabit per second rate serial backplane channel. This form of equalization scheme typically relies on a training sequence. However this training sequence may not be shared by all implementations of the DFE, thus causing significant compatibility issues. A model of a DFE and adaptation algorithm was developed in MATLAB in combination with measurement data of a typical backplane channel. A method was developed to process the incoming signals from the channel involving a known adaptation algorithm in order to determine appropriate tap coefficients. These coefficients are shown to be effective for a data rate of 10 Gbps. The design presented would yield itself to standard-cell implementation except for the analog DFE structure and several stages of the up/down counters. Furthermore the design was evaluated using representative error sources and across several design parameters.Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.There are many people I would like to thank for their encouragement and support during the course of my degree. The first and foremost is my supervisor, Professor Tad Kwasniewski, for always guiding me with my best interests in mind and for creating an environment which is so ideal for learning. I would like to thank my research group, from which I have learned a great deal more than I had ever anticipated. To my friends in the department;

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