The IBM 4769 Cryptographic Coprocessor

Busby, J. A.; Cohen, Efrat; Dames, E. A.; Doherty, Jim; Dragone, S.; Evans, D.; Fisher, Margaret; Hadzic, N.; Hagleitner, Christoph; Higby, A. J.; Hocker, M. D.; Jagich, L. S.; Jordan, M.; Kisley, R.; Lamb, Kara D.; Marik, M.; Mayfield, J.; Morris, Trevor; Needham, T. D.; Santiago-Fernandez, W.; Urban, Václav; Visegrady, T.; Klaus, Werner

doi:10.1147/jrd.2020.3008145

Cited by 3 publications

(1 citation statement)

References 3 publications

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“…Nevertheless, there are some common types of operations that happen across a wide range of applications. Such examples are data sorting [72], compression [2,109] or cryptography [18]. IBM Z has a long history of implementing hardware accelerators for such tasks in cooperation with the firmware and software teams to enable best possible end to end value from those accelerators.…”

Section: Introductionmentioning

confidence: 99%

AI accelerator on IBM Telum processor

Lichtenau

Buyuktosunoglu²,

Bertran³

et al. 2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

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IBM Telum is the next generation processor chip for IBM Z and LinuxONE systems. The Telum design is focused on enterprise class workloads and it achieves over 40% per socket performance growth compared to IBM z15. The IBM Telum is the first server-class chip with a dedicated on-chip AI accelerator that enables clients to gain real time insights from their data as it is getting processed.Seamlessly infusing AI in all enterprise workloads is highly desirable to get real business insight on every transaction as well as to improve IT operation, security, and data privacy. While it would undeniably provide significant additional value, its application in practice is often accompanied by hurdles from low throughput if run on-platform to security concerns and inconsistent latency if run off-platform. The IBM Telum chip introduces an on-chip AI accelerator that provides consistent low latency and high throughput (over 200 TFLOPS in 32 chip system) inference capacity usable by all threads. The accelerator is memory coherent and directly connected to the fabric like any other general-purpose core to support low latency inference while meeting the system's transaction rate. A scalable architecture providing transparent access to AI accelerator functions via a non-privileged general-purpose core * This paper is part of the Industry Track of ISCA 2022's program.

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Section: Introductionmentioning

confidence: 99%

AI accelerator on IBM Telum processor

Lichtenau

Buyuktosunoglu²,

Bertran³

et al. 2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

View full text Add to dashboard Cite

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Design and implementation of trusted boot based on a new trusted computing dual-architecture

Zheng¹,

Li²,

Yao³

2023

Computers & Security

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ShieldCXL: A Practical Obliviousness Support with Sealed CXL Memory

Choi,

Kim,

Lee

et al. 2024

ACM Trans. Archit. Code Optim.

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The CXL (Compute Express Link) technology is an emerging memory interface with high-level commands. Recent studies applied the CXL memory expanding technique to mitigate the capacity limitation of the conventional DDRx memory. Unlike the prior studies to use the CXL memory as the capacity expander, this study proposes to use the CXL-based memory as a secure main memory device, while removing the conventional memory. In the conventional DDRx memory, to provide confidentiality, integrity, replay protection, and obliviousness, costly mechanisms such as counter-based integrity trees and location shuffling by ORAM (Oblivious RAM) are used. Such mechanisms incur significant performance degradation in the current DDR-based memory systems, and their costs increase as the capacity of the memory increases. To mitigate the performance degradation, the prior work proposed an obfuscated channel for a secure memory module enclosing its controller in the package. Based on the approach, we propose a secure CXL-only memory architecture called ShieldCXL . It uses the channel encryption and integrity protection mechanism of the CXL interface to provide a practical ORAM while supporting confidentiality, integrity, and replay protection from physical attacks and rowhammers. To protect the PCIe-connected memory expanding board, this study proposes to use the standard physical sealing technique to detect physical intrusion. To mitigate the increased latency with the sealed CXL memory module, the study further optimizes performance by adopting an in-package DRAM cache. In addition, this study investigates destination obfuscation when a CXL switch is used to route among multiple hosts and memory devices. The evaluation shows that ShieldCXL provides 9.16x performance improvements over the prior ORAM technique.

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The IBM 4769 Cryptographic Coprocessor

Cited by 3 publications

References 3 publications

AI accelerator on IBM Telum processor

AI accelerator on IBM Telum processor

Design and implementation of trusted boot based on a new trusted computing dual-architecture

ShieldCXL: A Practical Obliviousness Support with Sealed CXL Memory

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