The impact of atomic layer depositions on high quality Ge/GeO&lt;inf&gt;2&lt;/inf&gt; interfaces fabricated by rapid thermal annealing in O&lt;inf&gt;2&lt;/inf&gt; ambient

Žurauskaitė, Laura; Hellström, Per‐Erik; Östling, Mikael

doi:10.1109/edtm.2017.7947553

Cited by 5 publications

(6 citation statements)

References 6 publications

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“…MOS capacitors (100×200 µm 2 ) were electrically characterized with capacitance-voltage (CV) measurements at 10 kHz frequency before and after FGA. Interface state density in the midgap was evaluated by comparing calculated CV characteristics with superimposed Dit distribution to the measured ones, as described in [12]. Oxide trap density was extracted from the hysteresis of dual CV sweep from inversion to accumulation and back.…”

Section: Methodsmentioning

confidence: 99%

Improvement on Ge/GeO_x/Tm₂O₃/HfO₂ Gate Performance by Forming Gas Anneal

Žurauskaitė

Östling

Hellström

2021

ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC)

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The improvement of forming gas anneal (10 % H2 in N2) at 400 °C on electrical properties of Ge/GeOx/Tm2O3/HfO2 gate stacks is investigated. It is found that forming gas anneal effectively suppresses fixed charge density, oxide trap density and interface state density. Hydrogen is demonstrated to efficiently passivate the negative fixed charge density and reduce the global variability of the flatband voltage down to 90 mV over a wafer. A forming gas anneal is also found to reduce equivalent oxide thickness in scaled gate stacks.

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Section: Methodsmentioning

confidence: 99%

Improvement on Ge/GeO_x/Tm₂O₃/HfO₂ Gate Performance by Forming Gas Anneal

Žurauskaitė

Östling

Hellström

2021

ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC)

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“…Electrical characterization of MOS capacitors was performed with Cascade 12000 wafer prober and Keithley SCS 4200. Interface state density in the midgap was evaluated from capacitance-voltage (CV) characteristics for 10 devices of each sample using a method described in (12).…”

Section: Methodsmentioning

confidence: 99%

Si-Passivated Ge Gate Stacks with Low Interface State and Oxide Trap Densities Using Thulium Silicate

et al. 2020

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Ultra-thin epitaxially grown Si layers have been used for Ge surface passivation in CMOS devices utilizing standard silicon SiO2/HfO2 gate stack. In this work, we propose a high-k TmSiO interfacial layer, which has shown excellent performance on Si, instead of the chemical SiO2. We successfully transfer a TmSiO/Tm2O3/HfO2 gate stack from silicon to Si-passivated Ge devices, yielding interface state density of 3·1011 eV-1cm-2, which is comparable to GeOx passivation. Moreover, Si-capped Ge gates with TmSiO interfacial layer achieve significant improvement in oxide trap density compared to GeOx passivation, exhibiting a potential for superior reliability. We further investigate the robustness of Si layer growth process and show that small (±3˚C) variations of growth temperature can be detrimental to the interface state density of the gate stacks.

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“…Interface state density in the midgap was evaluated from CV characteristics at 10 kHz for 10 devices (each on a separate die) of each sample using a method described in Ref. 16.…”

Section: Methodsmentioning

confidence: 99%

Process Conditions for Low Interface State Density in Si-passivated Ge Devices with TmSiO Interfacial Layer

Žurauskaitė¹,

Hellström

Östling

2020

ECS J. Solid State Sci. Technol.

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In this work we study the epitaxial Si growth with Si2H6 for Ge surface passivation in CMOS devices. The Si-caps are grown on Ge in the hydrogen desorption limited regime at a nominal temperature of 400 °C. We evaluate the process window for the interface state density and show that there is an optimal Si-cap thickness between 8 and 9 monolayers for Dit < 5·1011 cm−2 eV−1. Moreover, we discuss the strong impact of the Si-cap growth time and temperature on the interface state density, which arises from the Si thickness dependence on these growth parameters. Furthermore, we successfully transfer a TmSiO/Tm2O3/HfO2 gate stack process from Si to Ge devices with optimized Si-cap, yielding interface state density of 3·1011 eV−1 cm−2 and a significant improvement in oxide trap density compared to GeOx passivation.

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The impact of atomic layer depositions on high quality Ge/GeO<inf>2</inf> interfaces fabricated by rapid thermal annealing in O<inf>2</inf> ambient

Cited by 5 publications

References 6 publications

Improvement on Ge/GeO_x/Tm₂O₃/HfO₂ Gate Performance by Forming Gas Anneal

Improvement on Ge/GeO_x/Tm₂O₃/HfO₂ Gate Performance by Forming Gas Anneal

Si-Passivated Ge Gate Stacks with Low Interface State and Oxide Trap Densities Using Thulium Silicate

Process Conditions for Low Interface State Density in Si-passivated Ge Devices with TmSiO Interfacial Layer

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The impact of atomic layer depositions on high quality Ge/GeO<inf>2</inf> interfaces fabricated by rapid thermal annealing in O<inf>2</inf> ambient

Cited by 5 publications

References 6 publications

Improvement on Ge/GeOx/Tm2O3/HfO2 Gate Performance by Forming Gas Anneal

Improvement on Ge/GeOx/Tm2O3/HfO2 Gate Performance by Forming Gas Anneal

Si-Passivated Ge Gate Stacks with Low Interface State and Oxide Trap Densities Using Thulium Silicate

Process Conditions for Low Interface State Density in Si-passivated Ge Devices with TmSiO Interfacial Layer

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Improvement on Ge/GeO_x/Tm₂O₃/HfO₂ Gate Performance by Forming Gas Anneal

Improvement on Ge/GeO_x/Tm₂O₃/HfO₂ Gate Performance by Forming Gas Anneal