The impact of FinFET technology scaling on critical path performance under process variations

Abdelkader, Osama; Mostafa, Hassan; Abdelhamid, Hamdy; Soliman, Ahmed M.

doi:10.1109/iceac.2015.7352194

Cited by 4 publications

(3 citation statements)

References 8 publications

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“…Power versus threshold voltage with technology scaling. 24 be used to verify the correctness of the results. For 7 nm, the power at the nominal threshold value is lower than the 20 nm nominal threshold power by a factor of 0.43.…”

Section: Technology Scaling Roadmap For Finfet-based Fpga Clustersmentioning

confidence: 99%

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Technology Scaling Roadmap for FinFET-Based FPGA Clusters Under Process Variations

Abdelkader

El-Din

Mostafa

et al. 2017

J CIRCUIT SYST COMP

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The technology scaling impact on FinFET-based Field-Programmable Gate Array (FPGA) components (Flip-Flops and Multiplexers) and cluster metrics is evaluated for technology nodes starting from 20[Formula: see text]nm down to 7[Formula: see text]nm. Power consumption, delay and energy (Power Delay Product, or PDP) trends are reported with FinFET technology scaling. Cluster metrics are then evaluated based on three benchmarking circuits: 2-bit adder, 4-bit NAND and cascaded flip-flops chain. The study shows that power, delay and PDP of the FPGA cluster are improved as we scale down the technology. An example for improvement is that for 7[Formula: see text]nm 2-bit adder, circuit speed is 15% higher than its value at 20[Formula: see text]nm and PDP at 7[Formula: see text]nm is reduced by 43% compared to its value at 20[Formula: see text]nm. The impacts of temperature and threshold voltage variations on FPGA cluster performance are also reported after evaluating a 2-bit adder circuit as a benchmark which is then used to calculate the design constraints to meet 99.9% yield percentage.

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Section: Technology Scaling Roadmap For Finfet-based Fpga Clustersmentioning

confidence: 99%

“…PDP versus threshold voltage with technology scaling. 24 Technology Scaling Roadmap for FinFET-Based FPGA Clusters…”

Section: Technology Scaling Roadmap For Finfet-based Fpga Clustersmentioning

confidence: 99%

Technology Scaling Roadmap for FinFET-Based FPGA Clusters Under Process Variations

Abdelkader

El-Din

Mostafa

et al. 2017

J CIRCUIT SYST COMP

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“…Then, even FinFET circuits can become less robust due to transient faults [5]. The impact of these issues intensifies even more as technology scaling advance more in-depth in the nanometer regime, decreasing the reliability of the circuits and increasing the need to devise techniques to effectively deal with these controversies [6].…”

Section: Circuit Design For Improve the Reliabilitymentioning

confidence: 99%

Sleep Transistors to Improve the Process Variability and Soft Error Susceptibility

Zimpeck

Meinhardt

Artola

et al. 2019

2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

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This paper evaluates the potential of using the sleep transistor in FinFET logic cells to mitigate the process variability effects and the soft error susceptibility. The insertion of a sleep transistor improves up to 40.6% the delay variability and up to 12.4% the power variability. Moreover, the design with a sleep transistor became all logic cells investigated free of faults, independently of the supply voltage applied in the design.

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NBTI and HCI Aging Prediction and Reliability Screening During Production Test

Ren

et al. 2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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The impact of FinFET technology scaling on critical path performance under process variations

Cited by 4 publications

References 8 publications

Technology Scaling Roadmap for FinFET-Based FPGA Clusters Under Process Variations

Technology Scaling Roadmap for FinFET-Based FPGA Clusters Under Process Variations

Sleep Transistors to Improve the Process Variability and Soft Error Susceptibility

NBTI and HCI Aging Prediction and Reliability Screening During Production Test

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