The impact of RCA treatment of glass substrates on the properties of polycrystalline silicon thin film transistors

Awadelkarim, Osama O.; Wang, Y. Z.

doi:10.1016/s0167-9317(98)00288-3

Cited by 11 publications

(3 citation statements)

References 19 publications

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“…The n-doped silicon wafer ( 100 , 0.001-0.005 cm) was purchased from LG Siltron. The wafer was heated in a mixture of NH 4 OH and H 2 O 2 with a volume ratio of 4:3 at 75 • C for 30 min to prepare the negatively charged Si substrate [18,24]. The substrate was then immersed into the solution of TDA • HCl in order to prepare the SAM modified surface.…”

Section: Methodsmentioning

confidence: 99%

Fabrication of uniform and high resolution copper nanowire using intermediate self-assembled monolayers through direct AFM lithography

et al. 2012

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Electrochemical AFM lithography was used to directly fabricate copper nanowires. The copper ions were strongly reduced by a negative sample bias at the point where the AFM tip was localized, and copper metal wires were successfully fabricated following the direction of the electrical field of the bias. A TDA⋅HCl self-assembled monolayer (SAM) was found to play an important role as an intermediate layer for enhancing the capability of high resolution and complete development after the AFM lithographic process. The physical and electrical properties of the wires were analyzed by AFM, EFM, SEM, TEM and I-V measurement. The fabricated copper has promising potential for applications such as masks and interconnectors for nanoelectronic devices.

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Section: Methodsmentioning

confidence: 99%

Fabrication of uniform and high resolution copper nanowire using intermediate self-assembled monolayers through direct AFM lithography

et al. 2012

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“…The thickness of the substrates is ∼250 µm. The Si wafers were cleaned prior to processes using the Radio Corporation of America (RCA) [15] sequence at 75 • C: RCA1 [H 2 O : NH 4 OH : H 2 O 2 = 5 : 1 : 1 (volume)] solution followed by RCA2[H 2 O : HCl : H 2 O 2 = 5 : 1 : 1(volume)] solution and were then dipped in 5% HF for 10 s. For comparison purpose, a native oxide and a thermal oxide were used as the HJ interlayers. The native oxide layer was formed by Si natural oxidation as the freshly bare silicon surface is covered with a few monolayers (∼15 Å) of oxide upon exposure to air [16].…”

Section: Methodsmentioning

confidence: 99%

Electrical properties and carrier transport mechanisms of n-ZnO/SiO_x/n-Si isotype heterojunctions with native or thermal oxide interlayers

Song

Guo

2008

J. Phys. D: Appl. Phys.

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N-type ZnO/SiOx/n-type crystalline silicon isotype heterojunctions (HJs) have been prepared by magnetron sputtering. Native and thermal oxides were employed as the interlayer between the Si substrate and the ZnO film. Transmission electron microscopy and x-ray photoelectron spectroscopy revealed that an oxide layer was inserted in the HJ interface, with thickness of ∼1.2 nm (native oxide) and ∼2.0 nm (thermal oxide). Atomic force microscopy and x-ray diffraction spectroscopy showed that the ZnO film on the Si substrate consists of tightly packed grains with sizes in the range 50–150 nm and is c-axis preferred orientation. The electrical properties were characterized by current–voltage (I–V), capacitance–voltage (C–V) and current–voltage–temperature (I–V–T) measurements. By a comparison of the HJ properties, the n-ZnO/thermal oxide/n-Si HJs show improved electrical properties, with a fairly low leakage current and high rectification ratio, although the series resistance increased. Studies of fitting the I–V–T measurement data suggest that the tunnelling process is a dominant current transport mechanism for the n-ZnO/native or thermal oxide/n-Si HJs at an intermediate voltage range.

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“…However, to maintain a compatibility with glass substrate, a surface heating is thus needed; a crystallization induced by laser beam that limits the energy dissipation in the silicon material appeared to be the best solution. To minimize the potential pollution generated by the glass substrate, a diffusion barrier made of deposited silicon dioxide is optimized (7).…”

Section: Tfts Process Improvementsmentioning

confidence: 99%

Improvement of Silicon-Based Thin Film Transistor Performances by Modifying Technological Fabrication Process Steps: a Similar Approach with ULSI Technology

Bonnaud

Mohammed‐Brahim

2007

ECS Trans.

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el : +33 2 23 23 60 71The silicon based thin film transistors technological process evolution is governed by electrical performance improvements that are needed for the numerous fields of large area electronic applications. In fact, the electrical properties of the TFTs are directly linked to many aspects combining efforts to improve the process steps by several ways. All these approaches are similar to the ultra large scale integration technology (ULSI) ones. The goal of this paper is to highlight these similarities. After the presentation of the evolution during the last twenty years of the TFT processes, we will discuss on the common approaches between nano-and giga-electronics in order to show that their basic scientific principles are roughly the same.

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The impact of RCA treatment of glass substrates on the properties of polycrystalline silicon thin film transistors

Cited by 11 publications

References 19 publications

Fabrication of uniform and high resolution copper nanowire using intermediate self-assembled monolayers through direct AFM lithography

Fabrication of uniform and high resolution copper nanowire using intermediate self-assembled monolayers through direct AFM lithography

Electrical properties and carrier transport mechanisms of n-ZnO/SiO_x/n-Si isotype heterojunctions with native or thermal oxide interlayers

Improvement of Silicon-Based Thin Film Transistor Performances by Modifying Technological Fabrication Process Steps: a Similar Approach with ULSI Technology

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The impact of RCA treatment of glass substrates on the properties of polycrystalline silicon thin film transistors

Cited by 11 publications

References 19 publications

Fabrication of uniform and high resolution copper nanowire using intermediate self-assembled monolayers through direct AFM lithography

Fabrication of uniform and high resolution copper nanowire using intermediate self-assembled monolayers through direct AFM lithography

Electrical properties and carrier transport mechanisms of n-ZnO/SiOx/n-Si isotype heterojunctions with native or thermal oxide interlayers

Improvement of Silicon-Based Thin Film Transistor Performances by Modifying Technological Fabrication Process Steps: a Similar Approach with ULSI Technology

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Product

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Electrical properties and carrier transport mechanisms of n-ZnO/SiO_x/n-Si isotype heterojunctions with native or thermal oxide interlayers