2005
DOI: 10.1109/ted.2005.850632
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The Impact of Semiconductor Technology Scaling on CMOS RF and Digital Circuits for Wireless Application

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Cited by 74 publications
(33 citation statements)
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“…Although many system and circuit level techniques have been developed for digital circuits, the benefit of CMOS technology scaling has given major part of its efficiency enhancement. Even though the performance of RF circuits can benefit from the technology scaling, RF circuits do not benefit as much as digital circuits do [6]. This is mainly because their area and power efficiency is limited by the noise, matching, and linearity of active and passive devices.…”
Section: Introductionmentioning
confidence: 99%
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“…Although many system and circuit level techniques have been developed for digital circuits, the benefit of CMOS technology scaling has given major part of its efficiency enhancement. Even though the performance of RF circuits can benefit from the technology scaling, RF circuits do not benefit as much as digital circuits do [6]. This is mainly because their area and power efficiency is limited by the noise, matching, and linearity of active and passive devices.…”
Section: Introductionmentioning
confidence: 99%
“…Some of those factors, such as thermal noise, matching, and occupied area of active devices improve slightly with the technology scaling. However factors such as occupied area of passive device and linearity of the active device usually do not improve or even deteriorated with the technology scaling [6]. Also, the output power requirements, which apply to a power amplifier, make scaling difficult due to the smaller breakdown voltage in scaled technology.…”
Section: Introductionmentioning
confidence: 99%
“…However new design difficulties have arose due to this decreasing transistor dimensions [3]- [5]. As it will be demonstrated, once the delay-locked loop (DLL) architecture and size (number of cells) has been fixed, the actual dimensions of the DLL blocks have a great impact on the performance of the system.…”
Section: Introductionmentioning
confidence: 99%
“…INTRODUCTION During the last years the scaling of the CMOS technology has allowed the integration of full systems on a chip (SoC), including both the digital and analog blocks, as well as the RF front-end [1], [2]. However new design difficulties have arose due to this decreasing transistor dimensions [3]- [5]. As it will be demonstrated, once the delay-locked loop (DLL) architecture and size (number of cells) has been fixed, the actual dimensions of the DLL blocks have a great impact on the performance of the system.…”
mentioning
confidence: 99%
“…Assuming (2), to lower power dissipation the RF CMOS technology is scaled down, since the evolution of defined almost increases inversely with the minimum gate length, Lmin, because of in short channel regimes f T 1/Lmin [2]. In fact a clear trend toward better LNA performance for reduced designed CMOS technology nodes is observed in the literature and, more specifically, from the low-power design point of view [3]. Therefore, according (1), to compensate the reduction of g m and A V due to low-power requirements, the passives quality factor must be increased.…”
Section: Introductionmentioning
confidence: 99%