The impact of SOI MOSFETs on low power digital circuits

Tseng, Ying-Che; Chin, S.C.; Woo, J.C.S.

doi:10.1145/263272.263343

Cited by 2 publications

(1 citation statement)

References 10 publications

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“…SOI circuits have attractive properties as compared to bulk CMOS, such as reduced source-and drain-to-substrate capacitances, no body effect in series stacks of transistors and suitability for reduced operation for given performance [7], [8]. In addi- tion, due to reduced capacitances, SOI devices consume less power [9], [10]. Moreover, since transistors are isolated from each other by an insulator, they require smaller area.…”

Section: A Silicon-on-insulator (Soi)mentioning

confidence: 99%

Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect

Karandikar

Sapatnekar

2003

IEEE Trans. VLSI Syst.

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We present a technology mapping algorithm for implementing a random logic gate network in domino logic. The target technology of implementation is silicon-on-insulator (SOI). SOI devices exhibit an effect known as parasitic bipolar effect (PBE), which can lead to incorrect logic values in the circuit. Our algorithm solves the technology mapping problem by permitting several transformations during the mapping process in order to avoid PBE, such as transistor reordering, altering the way that transistors are organized into gates, and adding pMOS discharge transistors. We minimize the total cost of implementation, which includes discharge transistors required for correct functioning. Our algorithm generates solutions that reduce the number of discharge transistors required by 53% and reduces the size of the final solution by 6.3% on average. We compare our results with a modification of a current technology mapping algorithm for bulk CMOS domino logic that reduces the cost of the final solution and find that our algorithm outperforms this method.

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Section: A Silicon-on-insulator (Soi)mentioning

confidence: 99%

Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect

Karandikar

Sapatnekar

2003

IEEE Trans. VLSI Syst.

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Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect

Karandikar

Sapatnekar

2001

Proceedings of the 38th Conference on Design Automation - DAC '01

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We present a technology mapping algorithm for implementing a random logic gate network in domino logic. The target technology of implementation is Silicon on Insulator (SOI). SOI devices exhibit an effect known as Parasitic Bipolar Effect (PBE), which can lead to incorrect logic values in the circuit. Our algorithm solves the technology mapping problem by permitting several transformations during the mapping process in order to avoid the PBE, such as transistor reordering, altering the way transistors are organized into gates, and adding pmos discharge transistors. We minimize the total cost of implementation, which includes the discharge transistors required for correct functioning. Our algorithm generates solutions that reduce the number of discharge transistors needed by 44.23%, and reduces the size of the final solution by 11.66% on average.

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The impact of SOI MOSFETs on low power digital circuits

Cited by 2 publications

References 10 publications

Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect

Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect

Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect

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