The impacts of high tensile stress CESL and geometry design on device performance and reliability for 90nm SOI nMOSFETs

Impact of strain and source/drain engineering on the low frequency noise behaviour in n-channel tri-gate FinFETs

“…At the same time, a strong enhancement in performance of CMOS devices can be achieved by introducing strain-engineering techniques without adding major process complexity [5,6]. In [7], two categories of strain techniques have been distinguished: biaxial global strain, where stress is introduced across the whole wafer by epitaxial growth of a SiGe 'buffer layer' on top of the silicon substrate; and uniaxial local strain, based on the use of compressively strained (pMOS) or tensile (nMOS) dielectric layers (referred to as contact etch stop layer (CESL)) which are directly deposited around the gate after frond-end-ofline processing to give a stress along the channel.…”

Low-frequency noise in downscaled silicon transistors: Trends, theory and practice

“…Third, the lowfrequency noise in MOS transistors is higher than the noise in BJTs, as one can see in Figure 15. In this figure, the data are for 134 nMOS transistors from [22,47,48,49,50,51,72,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123], and for 53 pMOS transistors from [47,52,86,…”

“…We have collected data from [22,47,48,49,50,51,72,82,86,87,88,89,90,91,92,93,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,149] for nMOS transistors and from [47,52,86,88,94,95,96,97,100,102,104,105,109,124,125,126,…”

A Semi-Floating Gate Memory with Tensile Stress for Enhanced Performance

“…The employment of strain technologies in modern electronic devices to improve mobility and drive current has been developed for decades in advanced complementary metal-oxide-semiconductor (CMOS) transistors [10][11][12][13][14][15]. However, most of these technologies, such as embedded SiGe [10] and embedded Si:C [13], request complex process steps, making them not suitable or transferrable to a wider range of advanced processes.…”

“…However, most of these technologies, such as embedded SiGe [10] and embedded Si:C [13], request complex process steps, making them not suitable or transferrable to a wider range of advanced processes. Hence, the tensile-stress contact etch stop layer (CESL) has gained popularity for its simplicity as well as good reliability and has been integrated into the CMOS fabrication process [14][15][16][17][18][19].…”