The Implementation of a New All-Digital Phase-Locked Loop on an FPGA and Its Testing in a Complete Wireless Transceiver Architecture

Cell based synthesized low noise all digital frequency synthesizer, 0.13μm CMOS and FPGA implementations

“…Most of the ADPLL sub-circuits can be synthesized easily from the RTL language except for the DCO[35] [36] [37][38],[39] [40]. Most of the FPGA-based ADPLL uses the coordinate rotation digital computer (CORDIC) algorithm inside the FPGA and an digital-to-analog converter (DAC) to realize the DCO which limits the DCO output from a few KHz to tens of MHz.This chapter describes a fully-synthesized ADPLL in the FPGA from the Verilog language including the DCO.…”