The influence of non-stoichiometry on the switching kinetics of strontium-titanate ReRAM devices

Fleck, K.; Aslam, Nabeel; Hoffmann‐Eifert, Susanne; Longo, V Valentino; Roozeboom, F.; Kessels, W.M.M.; Böttger, U.; Waser, Rainer; Menzel, Stephan

doi:10.1063/1.4972833

Cited by 10 publications

(7 citation statements)

References 37 publications

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“…In this study, we propose a different failure mechanism limiting the RESET kinetics in the subnanosecond regime: For this purpose, we focus on the RESET kinetics in the regime from 50 ns to 50 ps and show that they are intrinsically limited by the presence of a unipolar switching mode. , Unlike previous studies, we also acquired a much larger data set to demonstrate the reproducibility of successful RESET operations. At slower time scales (above 700 ps) the RESET kinetics depend exponentially on the applied voltage, which was already demonstrated in other studies. ,− By increasing the applied voltage we could successfully reset the TaO x -based device within 670 ps at a voltage of 1.6 V and the ZrO x -based device within 480 ps at a voltage of 1.8 V. At higher voltages, the devices could not be driven to the HRS. Instead of an increase in resistance, a unipolar SET could be observed, decreasing the device’s resistance and, thereby, preventing faster RESET times.…”

Section: Introductionsupporting

confidence: 75%

“…To determine the RESET time from this current response, the beginning of the pulse and the RESET event need to be determined. In studies on slower time scales, the time at the end of the voltage pulse’s rising edge is often taken as the pulse’s beginning, , which is valid as long as the rise time is neglectable compared to the determined switching time. As this study investigates the RESET kinetics on a subnanosecond time scale, the RESET time is on a similar time scale than the pulse generator’s rise time (approximately 360 ps).…”

Section: Resultsmentioning

confidence: 99%

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Intrinsic RESET Speed Limit of Valence Change Memories

Witzleben

Wiefels

Kindsmüller

et al. 2021

ACS Appl. Electron. Mater.

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During the past decade, valence change memory (VCM) has been extensively studied due to its promising features, such as a high endurance and fast switching times. The information is stored in a high resistive state (HRS) and a low resistive state (LRS). It can also be operated in two different writing schemes, namely a unipolar switching mode (LRS and HRS are written at the same voltage polarity) and a bipolar switching mode (LRS and HRS are written at opposite voltage polarities). VCM, however, still suffers from a large variability during writing operations and also faults occur, which are not yet fully understood and, therefore, require a better understanding of the underlying fault mechanisms. In this study, a new intrinsic failure mechanism is identified, which prohibits RESET times (transition from LRS to HRS) faster than 400 ps and possibly also limits the endurance. We demonstrate this RESET speed limitation by measuring the RESET kinetics of two valence change memory devices (namely Pt/TaO x /Ta and Pt/ZrO x /Ta) in the time regime from 50 ns to 50 ps, corresponding to the fastest writing time reported for VCM. Faster RESET times were achieved by increasing the applied pulse voltage. Above a voltage threshold it was, however, no longer possible to reset both devices. Instead a unipolar SET (transition from HRS to LRS) event occurred, preventing faster RESET times. The occurrence of the unipolar SET is attributed to an oxygen exchange at the interface to the Pt electrode, which can be suppressed by introducing an oxygen blocking layer at this interface, which also allowed for 50 ps fast RESET times.

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Section: Introductionsupporting

confidence: 75%

Section: Resultsmentioning

confidence: 99%

Intrinsic RESET Speed Limit of Valence Change Memories

Witzleben

Wiefels

Kindsmüller

et al. 2021

ACS Appl. Electron. Mater.

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show abstract

“…Different to previous studies, we also acquired a much larger dataset to demonstrate the reproducibility of successful RESET operations. At slower timescales (above 700 ps) the RESET kinetics depend exponentially on the applied voltage, which was already demonstrated in other studies [28,[44][45][46][47]. By increasing the applied voltage we could successfully reset the TaO x -based device within 670 ps at a voltage of 1.6 V and the ZrO x -based device within 480 ps at an voltage of 1.8 V. At higher voltages, the devices could not be driven to the HRS.…”

Section: Introductionsupporting

confidence: 75%

Intrinsic RESET speed limit of valence change memories

von Witzleben,

Wiefels,

Kindsmüller

et al. 2021

Preprint

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During the last decade, valence change memory (VCM) has been extensively studied due to its promising features, such as a high endurance and fast switching times. The information is stored in a high resistive state (logcial '0', HRS) and a low resistive state (logcial '1', LRS). It can also be operated in two different writing schemes, namely a unipolar switching mode (LRS and HRS are written at the same voltage polarity) and a bipolar switching mode (LRS and HRS are written at opposite voltage polarities). VCM, however, still suffers from a large variability during writing operations and also faults occur, which are not yet fully understood and, therefore, require a better understanding of the underlying fault mechanisms. In this study, a new intrinsic failure mechanism is identified, which prohibits RESET times (transition from LRS to HRS) faster than 400 ps and possibly also limits the endurance. We demonstrate this RESET speed limitation by measuring the RESET kinetics of two valence change memory devices (namely Pt/TaOx/Ta and Pt/ZrOx/Ta) in the time regime from 50 ns to 50 ps, corresponding to the fastest writing time reported for VCM. Faster RESET times were achieved by increasing the applied pulse voltage. Above a voltage threshold it was, however, no longer possible to reset both types of devices. Instead a unipolar SET (transition from HRS to LRS) event occurred, preventing faster RESET times. The occurrence of the unipolar SET is attributed to an oxygen exchange at the interface to the Pt electrode, which can be suppressed by introducing an oxygen blocking layer at this interface, which also allowed for 50 ps fast RESET times.

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“…It is similar to the one used in refs. . The switching kinetics are assumed to be limited by the migration of doubly charged oxygen vacancies only, as this process is strongly temperature dependent.…”

Section: Discussionmentioning

confidence: 99%

Investigation of the Impact of High Temperatures on the Switching Kinetics of Redox‐Based Resistive Switching Cells using a High‐Speed Nanoheater

Witzleben

Fleck

Funck

et al. 2017

Adv Elect Materials

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Ionic transport greatly influences the switching kinetics of filamentary resistive switching memories and depends strongly on temperature and electric fields. To separate the impact of both parameters on the switching kinetics and to further deepen the understanding of the influence of local Joule heating, a nanometer‐sized heating structure is employed. It consists of a 100 nm wide Pt electrode which, due to Joule heating, serves as heating source upon an electrical stimulus. These self‐heating properties are underlined by a 3D finite elements simulation model, which confirms a temperature increase of almost 500 K. Experimental electrical pulse measurements indicate that for this temperature a steady state is achieved in less than 100 ns. By employing this heating structure, kinetic measurements of a Pt/Ta2O5/Ta cell are performed at different temperatures and reveal that significantly decreased SET times are obtained with increasing temperature. This effect is accompanied by an increasing slope of the current prior to the SET event. The experimental results are further confirmed by predictions of an analytical model based on ionic conduction.

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The influence of non-stoichiometry on the switching kinetics of strontium-titanate ReRAM devices

Cited by 10 publications

References 37 publications

Intrinsic RESET Speed Limit of Valence Change Memories

Intrinsic RESET Speed Limit of Valence Change Memories

Intrinsic RESET speed limit of valence change memories

Investigation of the Impact of High Temperatures on the Switching Kinetics of Redox‐Based Resistive Switching Cells using a High‐Speed Nanoheater

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