The influence of surface preparation on low temperature HfO2 ALD on InGaAs (001) and (110) surfaces

Abstract

Current logic devices rely on 3D architectures, such as the tri-gate field effect transistor (finFET), which utilize the (001) and (110) crystal faces simultaneously thus requiring passivation methods for the (110) face in order to ensure a pristine 3D surface prior to further processing. Scanning tunneling microscopy (STM), x-ray photoelectron spectroscopy (XPS), and correlated electrical measurement on MOSCAPs were utilized to compare the effects of a previously developed in situ pre-atomic layer deposition (ALD) surface clean on the InGaAs (001) and (110) surfaces. Ex situ wet cleans are very effective on the (001) surface but not the (110) surface. Capacitance voltage indicated the (001) surface with no buffered oxide etch had a higher C(max) hypothesized to be a result of poor nucleation of HfO2 on the native oxide. An in situ pre-ALD surface clean employing both atomic H and trimethylaluminum (TMA) pre-pulsing, developed by Chobpattana et al. and Carter et al. for the (001) surface, was demonstrated to be effective on the (110) surface for producing low D(it) high C(ox) MOSCAPs. Including TMA in the pre-ALD surface clean resulted in reduction of the magnitude of the interface state capacitance. The XPS studies show the role of atomic H pre-pulsing is to remove both carbon and oxygen while STM shows the role of TMA pre-pulsing is to eliminate H induced etching. Devices fabricated at 120 °C and 300 °C were compared.

High-throughput ab initio calculations on dielectric constant and band gap of non-oxide dielectrics

“…On the other hand, new channel materials such as Ge, InSb and InGaAs are considered for the next-generation semiconducting devices because intrinsic carrier mobilities are higher in these materials than in Si 9 . However, the interface between these materials and oxides, for instance Ge/GeO 2 and InGaAs/HfO 2 , are more defective than the Si/SiO 2 interface, degrading the carrier mobility in actual devices 14 – 17 . The foregoing discussions indicate that a more diverse library of high- k materials will be beneficial in coping with the challenges in next-generation semiconducting devices.…”

In Situ SiO2 Passivation of Epitaxial (100) and (110)InGaAs by Exploiting TaSiOx Atomic Layer Deposition Process

“…This approach has been successfully demonstrated using atomic layer deposited amorphous TaSiO x on (i) InP/InGaAs/InAlAs quantum well FETs, 3 (ii) InGaAs FinFETs, 4,5 and (iii) GaAsSb/InGaAs tunnel FETs. 9,10 Moreover, successful integration of high-κ dielectrics, for example., Al 2 O 3 , 11−13 HfO 2 14 and TaSiO x 3−5,15−18 on crystallographically oriented (100)In x Ga 1– x As and (110)In x Ga 1– x As would aid in paving the way for In x Ga 1– x As FinFET adoption, of which a representative device architecture is shown in Figure 1.…”

Lack of correlation between C-V hysteresis and capacitance frequency dispersion in accumulation of metal gate/high-k/n-InGaAs metal-oxide-semiconductor stacks

“…It should be pointed out that these samples are fabricated on (110) InGaAs substrates, where the nucleation and growth of Al 2 O 3 can produce different distribution of defects throughout the oxide and the bandgap. 45 This discussion highlights the impact of FGA on the C-V hysteresis of the sample, although there is a strong lack of correlation between widely accepted N bt indicators. 21,23 In this framework, while frequency dispersion probes only those defects located around the Fermi level, dynamic stress sweeps in hysteresis measurements reveal the full defect profile throughout the bandgap.…”