The Interpose PUF: Secure PUF Design against State-of-the-art Machine Learning Attacks

Nguyen, Phuong Ha; Sahoo, Durga Prasad; Jin, Chenglu; Mahmood, Kaleel; Rührmair, Ulrich; Dijk, Marten van

doi:10.46586/tches.v2019.i4.243-290

Cited by 122 publications

(79 citation statements)

References 19 publications

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“…3) Resistance against PUF modeling mechanisms: SVM, LR, and CMA-ES have been shown to be effective in attacking the arbiter-PUF and its derivatives (XOR-PUF, Feed-Forward PUF, etc) with high accuracy [19], [20]. Accordingly, this set of results investigates the resiliency of our proposed method against these modeling mechanisms.…”

Section: A Experimental Resultsmentioning

confidence: 98%

Countering PUF Modeling Attacks through Adversarial Machine Learning

Ebrahimabadi

Lalouani

Younis

et al. 2021

2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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A Physically Unclonable Function (PUF) is an effective option for device authentication, especially for IoT frameworks with resource-constrained devices. However, PUFs are vulnerable to modeling attacks which build a PUF model using a small subset of its Challenge-Response Pairs (CRPs). We propose an effective countermeasure against such an attack by employing adversarial machine learning techniques that introduce errors (poison) to the adversary's model. The approach intermittently provides wrong response for the fed challenges. Coordination among the communicating parties is pursued to prevent the poisoned CRPs from causing the device authentication to fail. The experimental results extracted for a PUF implemented on FPGA demonstrate the efficacy of the proposed approach in thwarting modeling attacks. We also discuss the resiliency of the proposed scheme against impersonation and Sybil attacks.

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Section: A Experimental Resultsmentioning

confidence: 98%

Countering PUF Modeling Attacks through Adversarial Machine Learning

Ebrahimabadi

Lalouani

Younis

et al. 2021

2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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“…Hence, total GE for 128‐bit CRC PUF is 1156. Interpose PUF proposed in [13] consists of one n ‐bit arbiter PUF and one ( n + 1) bit arbiter PUF.…”

Section: Simulation and Results Analysismentioning

confidence: 99%

“…In other words, the MARPUF is more resistant to ML attacks. We also compared the proposed MARPUF with other PUF schemes like CRC PUF [12], interpose PUF [13] , and Wang et al PUF [16] to evaluate the hardware cost and it is observed from Table 3 that the proposed MARPUF has the edge over the said PUF designs. Furthermore, MARPUF requires two clock cycles to generate the output as PUF response, which is higher than the conventional PUF like RO PUF and arbiter PUF designs, as MARPUF involves two rounds of operation.…”

Section: Discussionmentioning

confidence: 99%

MARPUF: physical unclonable function with improved machine learning attack resistance

Tripathy

Kumar

Mathew

2021

IET Circuits, Devices & Syst

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Nowadays, physical unclonable functions (PUFs) are emerging as one of the key building blocks for device authentication and key generation. Although PUF is very useful in the area of hardware security, it is vulnerable to machine learning modelling attacks (ML-MA) by modelling the challenge-response pairs (CRPs) behaviour. To this end, this study proposes a novel PUF named MARPUF, which gives good resistance to machine learning (ML) attacks. The study proposed a MARPUF design, where the mapping of CRPs is randomized by implementing two-round challenges to meet the randomness requirements for ML resistance. Ssome of the popular ML techniques are used to test the ML attack resistance and compare the results with some existing PUFs. We evaluate the performance of the PUF against various parameters like reliability, uniformity, uniqueness, etc. The hardware cost analysis shows that MARPUF requires lesser hardware than the existing ML-MA resistant PUFs. This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

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“…Our above GeniePUF architecture has been implemented on Xilinx Zynq FPGA with a so-called Interpose PUF or iPUF [28] as its underlying PUF. Interpose PUFs are constructed from Arbiter PUFs of variable length, and consist of several parallel layers of these Arbiter PUFs, similar to the well-known XOR Arbiter PUF architectures [45].…”

Section: Practicality and Performance Figures Of Our Constructionmentioning

confidence: 99%

“…Starting with the practical and implementational side, further optimization of our logical Erasable PUFs together with prototyping in FPGAs and ASICs seems a worthwhile endeavour. Other Strong PUFs than the iPUF [28] can be used in connection with the generic GeniePUF technique. On the theory side, our novel definitional framework will first of all hopefully spark a new style of easily acccessible, intuitive PUF-definitions in follow-up works.…”

Section: Summary and Future Workmentioning

confidence: 99%

Erasable PUFs

Jin

Burleson

Dijk

et al. 2020

Proceedings of the 4th ACM Workshop on Attacks and Solutions in Hardware Security

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Physical Unclonable Functions (PUFs) have not only been suggested as new key storage mechanism, but Ð in the form of socalled łStrong PUFsž Ð also as cryptographic primitives in advanced schemes, including key exchange, oblivious transfer, or secure multiparty computation. This notably extends their application spectrum, and has led to a sequence of publications at leading venues such as IEEE S&P, CRYPTO, and EUROCRYPT in the past [3,6,10,11,29,41]. However, one important unresolved problem is that adversaries can break the security of all these advanced protocols if they gain physical access to the employed Strong PUFs after protocol completion [41]. It has been formally proven [49] that this issue cannot be overcome by techniques on the protocol side alone, but requires resolution on the hardware level Ð the only fully effective known countermeasure being so-called Erasable PUFs [36]. Building on this work, this paper is the first to describe a generic method how any given silicon Strong PUF with digital CRP-interface can be turned into an Erasable PUF. We describe how the Strong PUF can be surrounded with a trusted control logic that allows the blocking (or łerasurež) of single CRPs. We implement our approach, which we call łGeniePUFž, on FPGA, reporting detailed performance data and practicality figures. Furthermore, we develop the first comprehensive definitional framework for Erasable PUFs. Our work so re-establishes the effective usability of Strong PUFs in advanced cryptographic applications, and in the realistic case adversaries get access to the Strong PUF after protocol completion. CCS CONCEPTS• Hardware → Integrated circuits; • Security and privacy → Embedded systems security.

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The Interpose PUF: Secure PUF Design against State-of-the-art Machine Learning Attacks

Cited by 122 publications

References 19 publications

Countering PUF Modeling Attacks through Adversarial Machine Learning

Countering PUF Modeling Attacks through Adversarial Machine Learning

MARPUF: physical unclonable function with improved machine learning attack resistance

Erasable PUFs

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