The intrinsic parameter fluctuation on high-κ/metal gate bulk FinFET devices

Li, Yiming; Su, Hung-Der; Chen, Yuyu; Hsu, Sheng-Chia; Huang, Wen-Tsung

doi:10.1016/j.mee.2013.03.076

Cited by 8 publications

(3 citation statements)

References 6 publications

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“…Thus it is expected that the intrinsic parameter fluctuation would affect the device performance at this nanometer scale, such as the threshold voltage fluctuation induced by random discrete dopants [25]. This threshold voltage fluctuation can be significantly reduced in bulk Fin-FETs as compared with the planar MOSFETs, which is attributed to the benefits of the 3D tri-gate structure [26].…”

Section: Resultsmentioning

confidence: 99%

Suppression of short channel effects in FinFETs using crystalline ZrO₂ high-K/Al₂O₃ buffer layer gate stack for low power device applications

Tsai

Wang

Chen

et al. 2018

Semicond. Sci. Technol.

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The electrical characteristics of FinFETs with a crystalline ZrO 2 /Al 2 O 3 buffer layer gate stack and a crystalline ZrO 2 high-K dielectric single layer, along with different fin widths and gate lengths, are investigated. Compared with the FinFETs with a single layer of crystalline ZrO 2 high-K dielectric, the gate stack comprising the crystalline ZrO 2 /Al 2 O 3 buffer layer on FinFETs leads to the suppression of short channel effects in terms of a low drain induced barrier lowering, reduced threshold voltage roll-off, and improved subthreshold swing. The ON/OFF current ratio and gate leakage current of FinFETs are also improved by the crystalline ZrO 2 /Al 2 O 3 buffer layer gate stack. The improvement of electrical characteristics is ascribed to the reduced interface state density and gate leakage as a result of the insertion of an Al 2 O 3 buffer layer between ZrO 2 and Si. The results demonstrate that the crystalline ZrO 2 /Al 2 O 3 buffer layer structure is a promising high-K gate stack for next-generation nanoscale transistors.

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Section: Resultsmentioning

confidence: 99%

Suppression of short channel effects in FinFETs using crystalline ZrO₂ high-K/Al₂O₃ buffer layer gate stack for low power device applications

Tsai

Wang

Chen

et al. 2018

Semicond. Sci. Technol.

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“…1(j) shows the trap's size of 2 x 2 nm 2 . Finally, we put the random generated ITs at HfO2/silicon film interface [21]. Similarly, we do generate RDF, WKF and ITF for the statistical device simulation of p-type bulk FinFET devices via the process of Figs.…”

Section: Statistical Device Simulation Of Intrinsic Parameter Fluctuamentioning

confidence: 99%

Statistical device simulation of intrinsic parameter fluctuation in 16-nm-gate n- and p-type Bulk FinFETs

Chen¹,

Huang²,

Hsu³

et al. 2013

2013 13th IEEE International Conference on Nanotechnology (IEEE-NANO 2013)

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In this paper, we estimate the influence of random dopants (RDs), interface traps (ITs), and random work functions (WKs) using the experimentally calibrated 3D device simulation on DC characteristic of high-κ / metal gate n-and p-type bulk fin-typed field-effect-transistors. We further study these intrinsic parameter fluctuations' impact on drain induced barrier lowering (DIBL). The main findings of this work show the RDF and WKF on n-type device are larger than that of p-type one. The DIBL is dominated by the number of random dopants.978-1-4799-0676-5/13/$31.00 ©2013 IEEE

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“…Except conventional variability issues, such as line end roughness, random dopant fluctuation, and workfunction fluctuation of metal gate grand in FinFET devices [15][16], new process variation sources in FinFET devices such as fin height fluctuation, gate height variation, contact height fluctuation, etc. cause device performance variation and timing uncertainty.…”

Section: Introductionmentioning

confidence: 99%

Design optimization of 16-nm bulk FinFET technology via geometric programming

2014

2014 International Workshop on Computational Electronics (IWCE)

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Design rule is an important interface between design and manufacturing. It becomes more complex as the process advances to 16-nm and beyond. Current approaches to generate design rules are empirical shrink and lithographic simulation. However, it is time-consuming and costly to revise design rules for performance boost and yield improvement after design rules are frozen. Early performance gains in early design rule development without cost increase and yield loss will benefit semiconductor industry. In this work, we for the first time consider 16-nm bulk FinFET standard cell performance, yield, area, and layout style simultaneously to optimize design rules to meet ITRS by using geometric programming. Optical proximity correction, and electromagnetic field and circuit simulations are performed for objective function evaluation. The result achieves more than 100%-delay and 50%-yield improvement without area change by this systematic and statistical approach.

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The intrinsic parameter fluctuation on high-κ/metal gate bulk FinFET devices

Cited by 8 publications

References 6 publications

Suppression of short channel effects in FinFETs using crystalline ZrO₂ high-K/Al₂O₃ buffer layer gate stack for low power device applications

Suppression of short channel effects in FinFETs using crystalline ZrO₂ high-K/Al₂O₃ buffer layer gate stack for low power device applications

Statistical device simulation of intrinsic parameter fluctuation in 16-nm-gate n- and p-type Bulk FinFETs

Design optimization of 16-nm bulk FinFET technology via geometric programming

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The intrinsic parameter fluctuation on high-κ/metal gate bulk FinFET devices

Cited by 8 publications

References 6 publications

Suppression of short channel effects in FinFETs using crystalline ZrO2 high-K/Al2O3 buffer layer gate stack for low power device applications

Suppression of short channel effects in FinFETs using crystalline ZrO2 high-K/Al2O3 buffer layer gate stack for low power device applications

Statistical device simulation of intrinsic parameter fluctuation in 16-nm-gate n- and p-type Bulk FinFETs

Design optimization of 16-nm bulk FinFET technology via geometric programming

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Product

Resources

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Suppression of short channel effects in FinFETs using crystalline ZrO₂ high-K/Al₂O₃ buffer layer gate stack for low power device applications

Suppression of short channel effects in FinFETs using crystalline ZrO₂ high-K/Al₂O₃ buffer layer gate stack for low power device applications