The inverse-narrow-width effect

Akers, L.A.

doi:10.1109/edl.1986.26422

Cited by 81 publications

(22 citation statements)

References 7 publications

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“…Another important reason for the small SNM improvement in AsymSize cell over Sym cell in Fig. 2 is that the V t decreases with the reducing device width in this technology due to the inverse-narrow width effect [8]. The reduced V t partly negates the effect from reduced device width.…”

Section: Read Stability Analysismentioning

confidence: 97%

Technology-circuit co-design of asymmetric SRAM cells for read stability improvement

Kim¹,

Rao²,

Kim³

2010

IEEE Custom Integrated Circuits Conference 2010

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We present asymmetric SRAM cell design approaches to improve Read stability over conventional symmetric SRAM Cell. We show that selective threshold voltage control is more effective than adjusting transistor size for read stability improvement in an asymmetric SRAM cell. We implement statistical DC noise margin monitors and present the hardware measurement data as well as the DC/AC simulation data to support the claims.

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Section: Read Stability Analysismentioning

confidence: 97%

Technology-circuit co-design of asymmetric SRAM cells for read stability improvement

Kim¹,

Rao²,

Kim³

2010

IEEE Custom Integrated Circuits Conference 2010

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“…It is known that threshold voltage (V T h ) and the current characteristics are different along the channel, which is the so-called "edge effect"-a type of inverse narrow width effect [8,9,10,11,12]. There are several factors causing the device threshold voltage to be non-uniform along the channel width, such as fringing capacitance due to line-end extension [10], dopant scattering due to shallow trench isolation (STI) edges [10], and the well proximity effect Fig.…”

Section: Trapezoidal Approximation Modelmentioning

confidence: 99%

Trapezoidal approximation for on-current modeling of 45-nm non-rectilinear gate shape

Ryu

Kim

2013

IEICE Electron. Express

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Abstract:In this paper, a simple and accurate modeling technique that analyzes a non-rectilinear gate (NRG) transistor with a simplified trapezoidal approximation method is proposed. To approximate a non-rectangular channel shape into a trapezoidal shape, we extract three geometry-dependent parameters from post-lithographic patterns: the minimum channel length from the slices (L min ), maximum channel length from the slices (L max ), and effective channel width (W ef f ). We slice the NRG transistor gate along its width, sort these slices according to their sizes, and then use trapezoidal approximation. A physics-based technology computer aided design (TCAD) simulation is used to verify our model in a typical 45-nm process. The developed model requires fewer computations and less runtime as compared to the previous approaches. Therefore, a full chip post-lithography analysis (PLA) becomes feasible.

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“…It has also been demonstrated that the minimum energy operation for CMOS circuits typically occurs in the subthreshold regime [1]. Owing to the inversenarrow-width effect (INWE), a transistor's threshold voltage lowers as the width narrows [2,3]. In subthreshold, this leads to larger than expected currents at these narrow widths owing to the exponential dependence of the subthreshold current on the threshold voltage.…”

mentioning

confidence: 99%

Designing digital subthreshold CMOS circuits using parallel transistor stacks

Muker

Shams

2011

Electron. Lett.

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A method for designing faster digital CMOS circuits operating in the subthreshold mode is proposed. Since the threshold voltage may be lower at narrower widths owing to the inverse-narrow-width effect in modern nanometre MOSFETs, the subthreshold current may be higher than expected at these narrow widths. It is shown that using only transistor widths that maximise the current-to-capacitance ratio, either individually or in parallel stacks, as appropriate, leads to faster circuits. Speed increases of up to 2.85 times have been demonstrated in ring oscillator simulations.Introduction: Battery-operated wireless and medical devices stress the importance of reduced power dissipation over high speed. Digital subthreshold circuit design has shown promise for low-power applications. The typically undesired parasitic subthreshold leakage current is used as the primary operation current in these circuits [1]. It has also been demonstrated that the minimum energy operation for CMOS circuits typically occurs in the subthreshold regime [1]. Owing to the inversenarrow-width effect (INWE), a transistor's threshold voltage lowers as the width narrows [2,3]. In subthreshold, this leads to larger than expected currents at these narrow widths owing to the exponential dependence of the subthreshold current on the threshold voltage. Transistors may also experience narrow-width effect (NWE), where the threshold voltage increases as the width narrows. Whether a transistor experiences INWE or NWE is specific to the technology kit, and may even vary between the PMOS and NMOS transistors within a given kit. Regardless of the specific behaviour, a design methodology to improve subthreshold performance has been developed. Although analytical expressions for the threshold voltage that account for the narrowwidth effects have been derived, they may prove unwieldy for subthreshold digital design. Thus this Letter demonstrates only a design methodology based on the transistor performance that takes advantage of the INWE present in nanometre CMOS technology kits.

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The inverse-narrow-width effect

Cited by 81 publications

References 7 publications

Technology-circuit co-design of asymmetric SRAM cells for read stability improvement

Technology-circuit co-design of asymmetric SRAM cells for read stability improvement

Trapezoidal approximation for on-current modeling of 45-nm non-rectilinear gate shape

Designing digital subthreshold CMOS circuits using parallel transistor stacks

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