The ITER interlock system

Fernandez-Hernando, J.L.; Carrillo, D.; Ciusa, G.; Liu, Y.; Prieto-diaz, Ignacio; Pedica, R.; Sayas, S.; Soni, J.; Vergara, A.

doi:10.1016/j.fusengdes.2018.02.059

Cited by 11 publications

(2 citation statements)

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“…Initially, an analysis was made of the clauses of IEC 61508-2 Annex-B and Annex-F to determine which are applicable or not to the system in question. In particular, Table I lists the amount of items from table "Techniques and measures to avoid introducing faults during E/E/PE system design and development" (Table B.2) and "Techniques and measures to avoid introducing faults during ASIC design and development: User programmable ICs (FPGA/PLD/CPLD)" (Table F.2) of the IEC 61508-2 standard [1], oriented to a SIL-3 target. For a clearer understanding, the items have been grouped into functionality subgroups.…”

Section: A Verification and Validation Planmentioning

confidence: 99%

“…HE fusion investment protection environments demand systems that protect the machine against serious damage caused by a failure in the plant systems or dangerous operation of the machine. The ITER system responsible for this function is the Interlock Control System (ICS) [1]. This system supervises and controls the different Plant Interlock Systems (PIS) and Advanced Protection System (APS), through the Central Interlock System (CIS), ensuring the integrity and availability of the machine.…”

Section: Introductionmentioning

confidence: 99%

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Verification and Validation of ITER Interlock System Fast Architecture According to IEC 61508 Standard

Garcia-Siguero

Ruiz

Barrera

et al. 2023

IEEE Trans. Nucl. Sci.

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The ITER Interlock Control System (ICS) requires the application of the IEC 61508 standard for all mission-critical (known as investment protection) control functions. Such functions must detect the events of the integrated physical processes and distribute them to the actuators with hard real-time constraints on the order of milliseconds or even microseconds. Systems able to achieve these timing requirements are often bespoke FPGA-based solutions, which are a well-known challenge to IEC 61508 processes. However, to minimize the variety of components and simplify the procurement process for an international supplier base, ITER decided to standardize the use of Commercial Off-The-Shelf (COTS) devices. The COTS selected for the ICS was the FPGAbased CompactRIO NI 9159 chassis (and several adapter I/O modules), provided by National Instruments (NI). This COTS requires the use of a high-level language (LabVIEW-FPGA) and the associated integrated development tools to develop the FPGA functionality. Therefore, it is necessary to ensure the required assurance that a COTS device is of sufficient quality, fit for purpose, and can be properly integrated into an investment protection control loop with the necessary level of systematic capability during the development process. This paper describes in detail the method ITER uses to perform the verification and validation according to the IEC 61508 standard recommendations, for the logic configuration generated by LabVIEW-FPGA for these COTS, after the compilation of high-level language sources designed during the development.

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Section: A Verification and Validation Planmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%