The J-Machine: A fine-grain parallel computer

Dally, William J.; Chien, Andrew A.; Davison, R.; Fiske, J.A.S.; Furman, S.; Fyler, G.; Gaunce, D.B.; Horwat, Waldemar; Kaneshiro, Shaun; Keen, John S.; Lethin, Richard; Noakes, Michael D.; Nuth, P.R.; Spertus, Ellen; Totty, Brian; Wallach, Deborah A.; Wills, D.S.

doi:10.1016/0956-0521(92)90089-2

Cited by 13 publications

(19 citation statements)

References 6 publications

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“…In the J-Machine [7], for example, node delay is 50 ns while the longest wire is 225 mm and has a time-of-flight delay of 1.5 ns. The channel width of these networks is often limited by node pin count rather than by wire bisection.…”

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confidence: 99%

Express cubes: improving the performance of k-ary n-cube interconnection networks

Dally

1991

IEEE Trans. Comput.

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182

136

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Abstruct-Express cubes are k-ary n-cube interconnection networks augmented by express channels that provide a short path for nonlocal messages. An express cube combines the logarithmic diameter of a multistage network with the wire-efficiency and ability to exploit locality of a low-dimensional mesh network. The insertion of express channels reduces the network diameter and thus the distance component of network latency. Wire length is increased allowing networks to operate with latencies that approach the physical speed-of-light limitation rather than being limited by node delays. Express channels increase wire bisection in a manner that allows the bisection to be controlled independent of the choice of radix, dimension, and channel width. By increasing wire bisection to saturate the available wiring media, throughput can be substantially increased. With an express cube both latency and throughput are wire-limited and within a small factor of the physical limit on performance. Express channels may be inserted into existing interconnection networks using interchanges. No changes to the local communication controllers are required.Index Terms-Communication networks, concurrent computing, interconnection networks, multicomputers, packet routing, packet switching, parallel processing, topology. An interconnection network is characterized by its topology, routing, and flow control [lo]. The topology of a network is the arrangement of its nodes and channels into a graph. Routing determines the path chosen by a message in this graph. Flow control deals with the allocation of channel and buffer resources to a message as it travels along this path. This paper deals only with topology. Express cubes can be applied independent of routing and flow control strategies. The performance of a network is measured in terms of its latency and its throughput. The latency of a message is the elapsed time from when the message send is initiated until the message is completely received. Network latency is the average message latency under specified conditions. Network throughput is the number of messages the network can deliver per unit time. Low-dimensional k-ary n-cube networks using wormhole routing have been shown to provide low latency and high throughput for networks that are wire-limited [4], [5], [9]. For n 3, the k-ary n-cube topology is wire-efficient in that it makes efficient use of the available bisection width. This topology maps into the three physical dimensions in a manner that allows messages to use all of the available bandwidth along their path without ever having to double back on themselves. Also, low-dimensional k-ary n-cubes concentrate bandwidth into a few wide channels so that the component of latency due to message length is reduced. In most contemporary concurrent computers, this is the dominant component of latency. Because of their low-latency, high throughput, and affinity for implementation in VLSI, these k-ary n-cube networks with n = 2 or 3 have been used However, low-dimensional k-ary n-cube intercon...

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confidence: 99%

Express cubes: improving the performance of k-ary n-cube interconnection networks

Dally

1991

IEEE Trans. Comput.

Self Cite

182

136

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“…GET requests contain the information necessary for the GET handler to reply with the appropriate PUT message. Note that it is possible to provide versions of PUT and GET that copy data blocks with a stride or any other form of gather/scatter 6 . To demonstrate the simplicity and performance of Split-C, Figure 4 shows a matrix multiply example that achieves 95% of peak performance on large nCUBE/2 configurations.…”

Section: Split-c: An Experimental Programming Model Using Active Messmentioning

confidence: 99%

“…This ability to suspend requires general allocation and scheduling on message arrival and is the key difference with respect to Active Messages. In the case of the J-Machine, the programming model is put forward in object-oriented language terms [6]: the handler is a method, the data holds the arguments for the method and usually one of them names the object the method is to operate on. In a functional language view, the message is a closure with a code pointer and all arguments of the closure.…”

Section: Intended Programming Modelmentioning

confidence: 99%

Active Messages: A Mechanism for Integrated Communication and Computation

Eicken

Culler

Goldstein

et al.

[1992] Proceedings the 19th Annual International Symposium on Computer Architecture

581

377

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The design challenge for large-scale multiprocessors is (1) to minimize communication overhead, (2) allow communication to overlap computation, and (3) coordinate the two without sacrificing processor cost/performance. We show that existing message passing multiprocessors have unnecessarily high communication costs. Research prototypes of message driven machines demonstrate low communication overhead, but poor processor cost/performance. We introduce a simple communication mechanism, Active Messages, show that it is intrinsic to both architectures, allows cost effective use of the hardware, and offers tremendous flexibility. Implementations on nCUBE/2 and CM-5 are described and evaluated using a split-phase shared-memory extension to C, Split-C. We further show that active messages are sufficient to implement the dynamically scheduled languages for which message driven machines were designed. With this mechanism, latency tolerance becomes a programming/compiling concern. Hardware support for active messages is desirable and we outline a range of enhancements to mainstream processors.

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“…The programs sequentially simulate the parallel execution of programs by a fine-grain message-passing parallel machine (which is described in [26]). …”

Section: Real-world Programsmentioning

confidence: 99%

Automated Program Recognition by Graph Parsing

Wills¹

1992

107

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JAN 22 1993_ 93-01046 93 J21 034- REPORT DOCUMENTATION PAGEForM N=o07-1 01MB NO 0704-0188 Pub•ic reporting burden for this collection of information is estimated to averaqe I hour oer response. including the time for revewing Instructions. searchrg e.-st'ng sata sour'., gathering and maintaining the data needed, and completing and reviewing the collection of information Send comments retarding this burden estimate or any other asoect Of this ol lection of information, including suggestions for reducing this burden, We demonstrate that this graph parsing approach is a feasible and useful way to automate program recognition. In studying this approach, we have experimented with two medium-sized, real-world simulator programs. There are three aspects of our study. First, we evaluate our representation's ability to suppress many common forms of program variation which hinder recognition. Second, we investigate the expressiveness of our graph grammar formalism for capturing programming cliches. Third, we empirically and analytically study the computational cost of our recognition approach with respect to the real-world simulator programs. The recognition of standard computational structures (cliches) in a program can help an experienced programmer understand the program. Based on the known relationships between the cliches, a hierarchical description of the program's design can be recovered. We develop and study a graph parsing approach to automating program recognition in which programs are represented as attributed dataflow graphs and a library of cliches is encoded as an attributed graph grammar. Graph parsing is used to recognize clich6s in the code. We demonstrate that this graph parsing approach is a feasible and useful way to automate program recognition. In studying this approach, we have experimented with two medium-sized, real-world simulator programs. There are three aspects of our study. First, we evaluate our representation's ability to suppress many common forms of program variation which hinder recognition. Second, we investigate the expressiveness of our graph grammar formalism for capturing programming clich6s. Third, we empirically and analytically study the computational cost of our recognition approach with respect to the real-world simulator programs.

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The J-Machine: A fine-grain parallel computer

Cited by 13 publications

References 6 publications

Express cubes: improving the performance of k-ary n-cube interconnection networks

Express cubes: improving the performance of k-ary n-cube interconnection networks

Active Messages: A Mechanism for Integrated Communication and Computation

Automated Program Recognition by Graph Parsing

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