The lithography technology for the 32 nm HP and beyond

Dusa, Mircea V.; Arnold, Bill Walter; Finders, Jo; Meiling, H.; Schenau, Koen van Ingen; Chen, Alek C.

doi:10.1117/12.796016

Cited by 12 publications

(5 citation statements)

References 12 publications

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“…An improvement of approximately 3% is observed at all levels of misalignment across the range tested. Dusa et al 3 reported that the registration observed between two layers of a double patterning process in the dense pattern structure was considerably better than the reported registration between the two layers using standard box-in-box alignment measurements. The simulated results are consistant with these practical observations although the magnitude of the simulated improvement is significantly less than the reported experimental effects.…”

Section: Rcwa Simulation Results With Embedded Topographymentioning

confidence: 95%

The modeling of double patterning lithographic processes

et al. 2007

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Double patterning (DP) appears to be the most probable patterning technology for initial 32 nm node manufacturing. This work explores how it may be accurately simulated. In the first instance, the process is approximated using two planar exposures in a commercial lithographic simulation package. This work is then followed up by more accurate calculations using a prototype simulator (based of Rigorous Coupled Wave Analysis propagation techniques) which allows the topography generated from the first exposure pass to influence the light propagation in the second exposure. The accuracy of the prototype simulator is demonstrated by validating its' output against the vector model in PROLITH V10, for the planar topography case. Results from the RCWA simulations show that for an example poly gate double patterning process, the presence of the topography enhances the process window of the second exposure, in terms of both exposure and focus latitude. The topography simulator is also used to study the robustness of the second exposure process window to fluctuations in the CD printed during the first exposure pass and of the influence of misalignment between the two passes.

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Section: Rcwa Simulation Results With Embedded Topographymentioning

confidence: 95%

The modeling of double patterning lithographic processes

et al. 2007

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“…The favorite industrial approaches for the patterning of nanoscale devices smaller than that limit are various kinds of double or even quadruple patterning. In Litho-Etch-Litho-Etch (LELE) [22] and Litho-Freeze-Litho-Etch (LFLE) [23] the number of features is doubled and the pitch size halved, by exposing the wafer twice with two different masks (e.g., the mask shifted by half the pitch for the second illumination), employing some memory process of the photoresist and finally developing the resist after the second illumination. Consequently, focus and especially dose variations are not correlated between these two incremental lithography steps.…”

Section: Resultsmentioning

confidence: 99%

Process Variability—Technological Challenge and Design Issue for Nanoscale Devices

et al. 2018

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Current advanced transistor architectures, such as FinFETs and (stacked) nanowires and nanosheets, employ truly three-dimensional architectures. Already for aggressively scaled bulk transistors, both statistical and systematic process variations have critically influenced device and circuit performance. Three-dimensional device architectures make the control and optimization of the device geometries even more important, both in view of the nominal electrical performance to be achieved and its variations. In turn, it is essential to accurately simulate the device geometry and its impact on the device properties, including the effect caused by non-idealized processes which are subject to various kinds of systematic variations induced by process equipment. In this paper, the hierarchical simulation system developed in the SUPERAID7 project to study the impact of variations from equipment to circuit level is presented. The software system consists of a combination of existing commercial and newly developed tools. As the paper focuses on technological challenges, especially issues resulting from the structuring processes needed to generate the three-dimensional device architectures are discussed. The feasibility of a full simulation of the impact of relevant systematic and stochastic variations on advanced devices and circuits is demonstrated.

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“…Possible candidates include contrast enhancement layer (CEL) 1 and two-photon absorption materials 2 . Figure 2b shows the logic extension of the litho-etch-litho-etch (LELE) 3 to litho-etch-litho-etchlitho-etch (LELELE). In this process, at least two hardmasks with good etch selectivity are required for pattern transfer.…”

Section: Higher Order Pitch Division Lithographymentioning

confidence: 99%

Analysis of higher order pitch division for sub-32nm lithography

Xie

Smith

2009

SPIE Proceedings

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The three knobs of optical lithography, namely process factor k 1 , wavelength (λ) and numerical aperture (NA) have been constantly pushed to print smaller features. To get an equivalent k 1 value below the fundamental limit of 0.25, double patterning (DP) has recently emerged as a viable solution for the 32nm lithography node. Various DP techniques exist such as litho-etch-litho-etch (LELE), litho-freeze-litho-freeze (LFLF) and self-aligned sidewall spacer. In this paper, the potential of higher order pitch division (pitch/N, N>2) for sub-32nm lithography is analyzed. Compared to double patterning, higher order pitch division lithography offers higher resolution but also faces significant challenges such as added cost and tighter process control. Several process schemes are proposed and compared in terms of complexity, susceptibility to alignment error and CD uniformity control. It is shown that the overlay budget does not necessarily decrease compared to double patterning. The main challenge in higher order pitch division comes from controlling the key processing steps that directly form lines or spaces. In addition, line CD control is easier than space (gap) control in all four "positive-tone" processes studied, similar to the double patterning case. Among the proposed processes, a freezing assisted double spacer (FADS) process that is simpler than the common sidewall spacer approach shows promise for balanced process control.

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The lithography technology for the 32 nm HP and beyond

Cited by 12 publications

References 12 publications

The modeling of double patterning lithographic processes

The modeling of double patterning lithographic processes

Process Variability—Technological Challenge and Design Issue for Nanoscale Devices

Analysis of higher order pitch division for sub-32nm lithography

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