The material optimization and reliability characterization of an indium-solder thermal interface material for CPU packaging

Deppisch, Carl; Fitzgerald, T. J.; Raman, Arun; Hua, Fay; Zhang, Charles; Liu, Pilin; Miller, Marisa E.

doi:10.1007/s11837-006-0186-6

Cited by 68 publications

(27 citation statements)

References 4 publications

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“…To acquire good thermal contact between the two surfaces, TIMs are put into practical use to fill the voids and grooves in imperfect surface finishes and improve the surface contact area. There are many types of conventional TIMs, such as thermal greases, phase change materials, and molten state solders . However, their heat transfer performance is also limited due to their relatively high bulk thermal resistance.…”

Section: New Methods To Control and Reduce The Itrmentioning

confidence: 99%

A Theoretical Review on Interfacial Thermal Transport at the Nanoscale

Zhang

Yuan

Xiong

et al. 2017

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109

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With the development of energy science and electronic technology, interfacial thermal transport has become a key issue for nanoelectronics, nanocomposites, energy transmission, and conservation, etc. The application of thermal interfacial materials and other physical methods can reliably improve the contact between joined surfaces and enhance interfacial thermal transport at the macroscale. With the growing importance of thermal management in micro/nanoscale devices, controlling and tuning the interfacial thermal resistance (ITR) at the nanoscale is an urgent task. This Review examines nanoscale interfacial thermal transport mainly from a theoretical perspective. Traditional theoretical models, multiscale models, and atomistic methodologies for predicting ITR are introduced. Based on the analysis and summary of the factors that influence ITR, new methods to control and reduce ITR at the nanoscale are described in detail. Furthermore, the challenges facing interfacial thermal management and the further progress required in this field are discussed.

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Section: New Methods To Control and Reduce The Itrmentioning

confidence: 99%

A Theoretical Review on Interfacial Thermal Transport at the Nanoscale

Zhang

Yuan

Xiong

et al. 2017

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109

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“…These results demonstrate that the plated indium layer has a high purity; carbon impurity analysis confirms this finding. Apart from thermal conductivity and CTE, it was demonstrated [4,5] that the IHS-Indium interface, thickness of indium layer, indium homogeneity and surface roughness all have a profound effect on the RTIM and the reliability performance of the whole package.…”

Section: Development Of New Indium Plating Bathmentioning

confidence: 99%

“…Gold facilitates wetting, while nickel serves as a barrier layer to indium. It was found [5] that the gold layer dissolves in indium and forms a brittle intermetallic which upon thermal cycling causes cracking and voiding.…”

Section: Development Of New Indium Plating Bathmentioning

confidence: 99%

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High-speed indium electrodeposition: Efficient, reliable TIM technology

Szőcs¹,

Schwager²,

Toben

et al. 2008

2008 2nd Electronics Systemintegration Technology Conference

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Formation of an efficient thermal path is very important for thermal management. Besides high thermal conductivity, several other properties are also important, for example: Current technology applies pre-formed sections of indium [4,5], but production issues arise from the required inspection, handling, and fluxing steps. Yield and performance suffer from interfacial shortcomings of a foil-based technology [6]. On the other hand, electrolytic deposition may produce high purity indium deposits with good interfacial characteristics suitable for use in TIM applications. Thick, uniform, pure indium layers are required which satisfy the above mentioned criteria. Several trials were conducted to plate pure indium from alkaline and acidic media [7,8,9,10], but very few electroplating baths are commercially available, and those have a high metal content and low plating rate. Our new plating technology overcomes these disadvantages; higher speed, better throwing powers as well as reliable plated finishes are obtained. Die Copper PCB PadCopper Pillar Bump ability to relax thermal expansion stresses when joining two materials ability to form a void-free, micro-crack-free joint that is stable during thermal cycling lack of sensitivity to moisture and temperature changes manufacturing feasibility cost.•A new indium electroplating process was developed which provides pure indium deposits suitable as thermal interface materials (TIM) in electronic industry. The main goals of the project were: i.) to develop a stable, high speed indium plating process; ii.) to obtain pure indium deposits with a low melting point (] 56°C) and high thermal conductivity (82 W/m-K); iii.) to provide good adhesion to the substrate with a void-free interface.The electrochemical plating bath is based on an acidic electrolyte with copolymer additives. Typical plating conditions are: pH 0.9-].2, current density 0.5-20ASD, temperature 30-60°C and a metal ion concentration of 30-60g/l. Uniform deposit thicknesses of a few microns up to several hundred microns can be achieved at a plating rate of 180 microns per hour at a current density of 10ASD. Good adhesion to standard nickel-plated substrates (no delamination or voids allowed) is critical for meeting the thermal and reliability targets. Adherent, void-free deposits were obtained with thermal conductivity and thermal expansion data that correspond favourably to literature values for the bulk metal.

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“…Internal thermal management should be done during the structure design process, and it plays a significant role. External thermal management includes the selection of the cooling mode, heat sink design, and the selection of a substrate, chip, and die-attach material [4,5]. The die-attach material, also called thermal-interface material (TIM), connects the different parts by filling the contact interface between them as a thermal-management solution.…”

Section: Introductionmentioning

confidence: 99%

Effects of some factors on the thermal-dissipation characteristics of high-power LED packages

Ji¹,

Moon²

2012

Journal of Information Display

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Decreasing the thermal resistance is the critical issue for high-brightness light-emitting diodes. In this paper, the effects of some design factors, such as chip size (24 and 35 mil), substrate material (AlN and high-temperature co-fired ceramic), and dieattach material (Ag epoxy and PbSn solder), on the thermal-dissipation characteristics were investigated. Using the thermal transient method, the temperature sensitivity parameter, R th (thermal resistance), and junction temperature were estimated. The 35-mil chip showed better thermal dissipation, leading to lower thermal resistance and lower junction temperature, owing to its smaller heat source density compared with that of the 24-mil chip. By adopting an AlN substrate and a PbSn solder, which have higher thermal conductivity, the thermal resistance of the 24-mil chip can be decreased and can be made the same as that of the 35-mil chip.

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The material optimization and reliability characterization of an indium-solder thermal interface material for CPU packaging

Cited by 68 publications

References 4 publications

A Theoretical Review on Interfacial Thermal Transport at the Nanoscale

A Theoretical Review on Interfacial Thermal Transport at the Nanoscale

High-speed indium electrodeposition: Efficient, reliable TIM technology

Effects of some factors on the thermal-dissipation characteristics of high-power LED packages

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