“…Introducing pores in a dielectric poses several challenges for successful integration into microelectronic circuits [17,18]. The mechanical strength of the dielectric is reduced by porosity, potentially leading to failure during chemical mechanical planarization (CMP) [19,20,21,22] or during wire bonding to the fi nished chip [23]. In addition, moisture, wet chemicals and gaseous species (such as precursors used during CVD) can penetrate into porous low-k materials, giving rise to an increase in both the dielectric constant and the leakage current [24].…”