The MU5 Computer System

Morris, Derrick; Ibbett, Roland N.

doi:10.1007/978-1-349-16103-4

Cited by 41 publications

(9 citation statements)

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“…Early machines, such as the CDC 6600 [Thornton 1970] and MU5 [Morris and Ibbett 1979], incorporated complex control mechanisms in an attempt to maximize the pipeline throughput. Studies of MU5 revealed that average instruction times were between 0.2 and 0.4/~s, compared with a pipeline beat time of 50ns.…”

Section: Discussionmentioning

confidence: 99%

“…The Branch Target Cache (BTC) is an alternative to the BTB and has attracted some attention recently; it has been studied in depth [Hill 1987] and implemented in at least one machine, the AMD 29000 microprocessor [AMD 1987]. A BTC differs from a BTB in that it stores instructions at the jump-to address rather than the address itself; such a system was considered for MU5 [Morris and Ibbett 1979] but was rejected on cost/performance grounds.…”

Section: '9mentioning

confidence: 99%

“…A quite different approach to high speed buffering was taken in the design of the MU5 computer [Ibbett 1982, Morris andIbbett 1979]. An examination of the operands used in high-level languages and studies of programs run on Atlas (the predecessor to MU5 at the University of Manchester) had indicated that over a large range of programs, 80% of all operand accesses were to named scalar variables, of which only a small number was in use at any one time.…”

Section: Block From Main Storagementioning

confidence: 99%

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On the design and performance of conventional pipelined architectures

Topham

Omondi

1988

J Supercomput

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Pipelining is a widely used technique for implementing architectures that have inherent temporal parallelism when there is an operational requirement for high throughput. Many variations on the basic theme have been proposed, with varying degrees of success. The aim of this paper is to present a critical review of conventional pipelined architectures and put some well-known problems in sharp relief. It is argued that conventional pipelined architectures have underlying limitations that can only be dealt with by adopting a different view of pipelining. These limitations are explained in terms of discontinuities in the flow of instructions and data, an d representative machines are examined in support of this argument. In a companion paper [Topham, Omondi and Ibbett, 1988] we examine an alternative approach to the design of pipelined architectures and introduce an alternative theory of pipelining, which we call Context Flow.

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Section: Discussionmentioning

confidence: 99%

Section: '9mentioning

confidence: 99%

Section: Block From Main Storagementioning

confidence: 99%

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On the design and performance of conventional pipelined architectures

Topham

Omondi

1988

J Supercomput

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“…The organization of the Branch Target Cache (BTC) is shown in Figure 5; it is similar to the 'Jump Trace Buffer' used on the MU5 mainframe computer [11] developed at the University of Manchester between 1969 and 1974 (which also operated with asynchronous control).…”

Section: The Branch Target Cachementioning

confidence: 99%

AMULET2e: an asynchronous embedded controller

Furber

Garside²,

Riocreux

et al. 1999

Proc. IEEE

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“…Whereas previous instruction pipelines, such as the primary operand pipeline in MU5 [Morris and Ibbett 1979], had pipeline stages that evaluated a function f such that f: Instruction w. Partial Result, the HEP pipeline stages evaluate a function g such that g:Instruction • Process Tag ~ Partial Result • Process Tag.…”

Section: Kaminsky Anddavidson's Workmentioning

confidence: 99%

Context flow: An alternative to conventional pipelined architectures

Topham

Omondi

1988

J Supercomput

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In an earlier paper [Topham, Omondi, and Ibbet 1988] we reviewed conventional approaches to the design of conventional pipelined architectures and concluded that the underlying limitations of these techniques necessitate radical alternatives. This paper discusses one such alternative, micromultiprogramming, and examines several implementation proposals based on this approach. The weaknesses of these proposals are highlighted, and it is argued that they can be eliminated within the unifying theory of context flow architectures. Implementations of uniprocessor and multiprocessor context flow architectures are considered. MicromultiprogrammingFor many years multiprogramming has been used as a technique for optimizing the utilization of a shared CPU and for providing an interactive multiuser capability. To get reasonable utilization, the time slice allocated to each process must be large in comparison with the time taken to change context. Therefore, multiprogramming at the operating system level is useful only for reducing inefficiencies caused by relatively severe discontinuities, typically I/O and memory management.However, there are discontinuities with much finer levels of granularity than this [Topham, Omondi, and Ibbett 1988]. For example, when an instruction within a pipeline needs an operand from main store, a pipeline discontinuity normally occurs. The latency associated with this discontinuity is typically of the order of several clock periods, and frequent operand accesses result in poor performance. It is often impossible to continue processing instructions from the same instruction stream when this happens, and so an alternative strategy must be adopted.One strategy that has been suggested, and used in at least one commercial machine, is micromultiprogramming. This is based on a recognition of the fact that a highlatency memory cycle and a high-latency I/O operation are simply two examples of 29

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The MU5 Computer System

Cited by 41 publications

References 0 publications

On the design and performance of conventional pipelined architectures

On the design and performance of conventional pipelined architectures

AMULET2e: an asynchronous embedded controller

Context flow: An alternative to conventional pipelined architectures

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