The multi-rate Iterated Timing Analysis algorithm for circuit simulation

Abstract

In circuit simulation, Relaxation-based algorithms have been proven to be faster and more flexible than the standard direct approach used in SPICE. ITA (Iterated Timing Analysis) algorithm has even been widely used in industry. This paper describes accelerating techniques that enable ITA to utilize circuits' multi-rate behaviors. These techniques are based on the latency property of subcircuits and the Strength of Signal Flow (SSF) between subcircuits. A more powerful technique using both latency and SSF is also proposed. Experimental examples are given to justify the superior properties of proposed methods.

Parallel Circuit and Transient Sensitivity Simulations by Using Combining Simulation Method

“…In the latter case, CSM constructs the distributed circuit simulation. In this paper, we just implement CSM in the multiple-core PC and only use our simulator (MOSTIME [3,5,6]). Experiments will be described later.…”

“…Such overhead is called "IO time" here, which will be recorded in our experiments. In using ITA, the points in time waveforms are usually dense [6]. This is due to that, in ITA, global time points are used for all subcircuits.…”

“…Dense time points cause big waveform files. This problem can be alleviated by using the Multi-rate ITA [6]. Also, reducing time points of ITA waveforms can further reduce sizes of waveform files and hence to reduce the IO time.…”

“…CPU TIME COMPARISON FOR ITA The used CPU is Intel Core i7 (1.73 GHZ) that has eight cores $: The used algorithm version is the so-called Multi-rate ITA[6] …”

A Class of Multirate Infinitesimal GARK Methods

“…Multirate time integration has been adopted by many applications including the simulation of electronic circuits [20,8], subsurface flows [1], ocean modeling [12,46], energy conversion [36], multibody dynamics [4], electromagnetic fields [16], and fluids in complex geometries [35], to name just a few.…”