The multi-threaded, parity-protected 128-word register files on a dual-core Itanium-family processor

Abstract

Multi-threaded microprocessors require multiple sets of register files to process concurrent instruction streams. This significantly complicates the register-file (RF) design and exacerbates reliability problems. This paper describes the dual-threaded, 18-port (8-read, 10-write), 128word × 82b floating-point register file (FRF), and the 22-port (12-read, 10-write), 128 × 65b integer register file (IRF) of the processor-code named Montecito [1]. A memory circuit is designed that consists of two storage cells, each bit accessible by two different threads. A charge-compensation technique is introduced to mitigate charge-sharing noise induced by threadswitch events. The dual-threaded implementation essentially doubles the number of memory cells and the RF becomes even more susceptible to errors caused by high-energy particles. A low-complexity parity-checking scheme is embedded into each register to provide soft error detection. The current design also integrates several power-saving features to achieve energy-efficiency and reliable operation.To support dual-threaded execution, each register bitcell incorporates two identical storage cells (Fig. 20.5.1). A control signal WRITEH is driven high during write operations, reducing the contention between the two cross-coupled inverters. Four transmission gates determine the thread selection, where each storage cell is exclusively accessible by either thread. Switching threads can induce charge-sharing noise between the storage cells b0/b1 and the internal bitlines ida/idb. Consider the worst-case scenario where the two storage cells contain different voltages. Each internal bitline will have the same voltage as the storage cell it is connected to. A thread switch is performed by flipping the thread signal. Each storage cell is then connected to the internal bitline having a different voltage value. Charge is redistributed momentarily between the storage cells and the internal bitlines. This may flip the storage cells and cause logic failures. To prevent this problem, two charge-compensation pFETs p0/p1 are introduced. The signal writel, connected to the sources of p0/p1, remains high during thread switch, thereby compensating for possible charge loss at b0/b1 through p0/p1 (Fig. 20.5.2). This technique does not induce additional contention during write operations when writel switches to virtual ground. Moreover, this technique improves write timing. A high voltage at the storage node (b0/b1) will be pulled down slightly by writel at the beginning of a write operation, making it easier to write a "0". For writing a "1", the chargecompensation pFETs p0/p1 help boost b0/b1 to VDD quickly at the end of a write when writel goes high.The register files are relatively large because of the dual-threaded implementation. This compounded with the high-density layout makes the RFs susceptible to soft errors. Therefore, the RF data arrays integrate parity checking hardware (Fig. 20.5.3) to provide soft error detection. Parity generation logic is embedded locally inside each register. ...

Making register file resistant to power analysis attacks

“…The address decoder selects the target register cells according to the register address and asserts the corresponding wordlines. Each register cell is an SRAM cell with multiple read/write ports [5] (2r/1w in this example). During a read operation, the wordline W L r 1 or W L r 2 is asserted, and the data stored in the selected register are evaluated by the read bitlines.…”

Montecito: A Dual-Core, Dual-Thread Itanium Processor

“…Moreover, this growth, though mainly in the already large register files, does not affect the register file and bypass network's critical paths because Montecito includes a memory cell in which two storage cells share bit lines. 7 …”

“…Itanium processors are already known for their outstanding reliability, availability, and serviceability (RAS), but Montecito expands the Itanium 2 RAS by providing protection for every major processor memory array from the register file 7 to the TLBs and caches.…”

“…The criticality and size also enabled the use of Pellston technology, 11 which maintains availability in the face of hard errors developed in the L3 cache while providing a mechanism for Montecito to scrub detected errors. Montecito also has parity protection for the register files (both integer and floating point), 7 temporary system interface data, and L2I data and tag bits. Parity protects some noncritical elements as well, such as branch-prediction structures and some cache-replacement structures.…”