1996
DOI: 10.1006/jpdc.1996.0033
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The Network Architecture of the Connection Machine CM-5

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Cited by 254 publications
(121 citation statements)
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“…The CM5 is a massively parallel computer based on 32MHz SPARC processors with a fat-tree interconnection network [32]. The Cilk runtime system on the CM5 performs communication among processors using the Strata [7] active-message library.…”
Section: Written By Chris Joerg Of Mit' S Laboratory For Computer Scimentioning
confidence: 99%
“…The CM5 is a massively parallel computer based on 32MHz SPARC processors with a fat-tree interconnection network [32]. The Cilk runtime system on the CM5 performs communication among processors using the Strata [7] active-message library.…”
Section: Written By Chris Joerg Of Mit' S Laboratory For Computer Scimentioning
confidence: 99%
“…For traditional parallel programming on tightly coupled multiprocessors, barriers are commonly used to separate phases of computation within an execution and form natural synchronization points [Jordan 1978]. Given the importance of fast primitives for coordinating bulk synchronous SIMD applications, most massively parallel processors (MPPs) have hardware support for barriers [Leiserson et al 1996;Scott 1996]. Barriers also form a natural consistency point for software distributed shared memory systems, often signifying the point where data will be synchronized with remote hosts [Keleher et al 1994;Bershad et al 1993].…”
Section: Synchronizationmentioning
confidence: 99%
“…The k-ary n-tree network [8], also called fat tree, is commonly used to optimize this network design by combining the crossbars in the middle. Those networks have very similar properties to Clos networks, and k-ary n-tree networks can be built with full bisection bandwidth like Clos networks.…”
Section: Clos Topologymentioning
confidence: 99%