The network architecture of the Connection Machine CM-5 (extended abstract)

Leiserson, Charles E.; Abuhamdeh, Zahi S.; Douglas, David C.; Feynman, Carl R.; Ganmukhi, Mahesh N.; Hill, Jeffrey V.; Hillis, Daniel; Kuszmaul, Bradley C.; Pierre, Margaret A. St.; Wells, David S.; Wong, Monica C.; Yang, Shaw-Wen; Zak, Robert

doi:10.1145/140901.141883

Cited by 220 publications

(27 citation statements)

References 11 publications

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“…Perhaps most closely related to our efforts are various efforts in building scalable interconnects, largely coming out of the supercomputer and massively parallel processing (MPP) communities. Many MPP interconnects have been organized as fat-trees, including systems from Thinking Machines [31,22] and SGI [33]. Thinking Machines employed pseudo-random forwarding decisions to perform load balancing among fat-tree links.…”

Section: Related Workmentioning

confidence: 99%

A scalable, commodity data center network architecture

Al-Fares

Loukissas

Vahdat

2008

SIGCOMM Comput. Commun. Rev.

2,012

1,098

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Today's data centers may contain tens of thousands of computers with significant aggregate bandwidth requirements. The network architecture typically consists of a tree of routing and switching elements with progressively more specialized and expensive equipment moving up the network hierarchy. Unfortunately, even when deploying the highest-end IP switches/routers, resulting topologies may only support 50% of the aggregate bandwidth available at the edge of the network, while still incurring tremendous cost. Nonuniform bandwidth among data center nodes complicates application design and limits overall system performance.In this paper, we show how to leverage largely commodity Ethernet switches to support the full aggregate bandwidth of clusters consisting of tens of thousands of elements. Similar to how clusters of commodity computers have largely replaced more specialized SMPs and MPPs, we argue that appropriately architected and interconnected commodity switches may deliver more performance at less cost than available from today's higher-end solutions. Our approach requires no modifications to the end host network interface, operating system, or applications; critically, it is fully backward compatible with Ethernet, IP, and TCP.

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Section: Related Workmentioning

confidence: 99%

A scalable, commodity data center network architecture

Al-Fares

Loukissas

Vahdat

2008

SIGCOMM Comput. Commun. Rev.

2,012

1,098

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“…RELATED WORK Fat-Tree Networks: Fat trees have been used for decades in the HPC field. Perhaps the most famous example is the Thinking Machines CM-5 [6]. The CM-5 used proprietary 8-port switch ASICs with a custom frame format.…”

Section: B Implementationmentioning

confidence: 99%

“…But as the number of packet switches grows, so does the cabling complexity and the difficulty of actually constructing the network, especially on a tight schedule and with a minimum amount of human error. Fat trees have been used successfully in telecom networks [5], HPC networks [6], and on chips [7], but not yet in data center Ethernet networks. One reason is the fear of the resulting cabling complexity from trying to interconnect thousands of individual switches and the overhead of managing a large number of individual switch elements.…”

Section: Introductionmentioning

confidence: 99%

Data Center Switch Architecture in the Age of Merchant Silicon

Farrington

Rubow

Vahdat

2009

2009 17th IEEE Symposium on High Performance Interconnects

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Abstract-Today, data center networks that scale to tens of thousands of ports require the use of highly-specialized ASICs, with correspondingly high development costs. Simultaneously, these networks also face significant performance and management limitations. Just as commodity processors and disks now form the basis of computing and storage in the data center, we argue that there is an opportunity to leverage emerging high-speed commodity merchant switch silicon as the basis for a scalable, cost-effective, modular, and more manageable data center network fabric. This paper describes how to save cost and power by repackaging an entire data center network as a distributed multi-stage switch using a fat-tree topology and merchant silicon instead of proprietary ASICs. Compared to a fat tree of discrete packet switches, a 3,456-port 10 Gigabit Ethernet realization of our architecture costs 52% less, consumes 31% less power, occupies 84% less space, and reduces the number of long, cumbersome cables from 6,912 down to 96, relative to existing approaches.

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“…Network designs: The history of on-chip networks begins with off-chip, large-scale system interconnects. This previous art used a variety of topologies, amongst them the ones we will include in our study: fat tree [20], butterfly [6], mesh [6] and ring [6]. Present and future multi-core designs demand much more than a simple integration of earlier large-scale system interconnects onto a single die.…”

Section: Introductionmentioning

confidence: 99%

Polymorphic On-Chip Networks

Davis¹,

Oskin²,

Austin³

2008

2008 International Symposium on Computer Architecture

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As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We begin this study with an area-performance analysis of the interconnect design space. We find that there is no single network design that yields optimal performance across a range of traffic patterns. This indicates that there is an opportunity to gain performance by customizing the interconnect to a particular application or workload.We propose polymorphic on-chip networks to enable perapplication network customization. This network can be configured prior to application runtime, to have the topology and buffering of arbitrary network designs. This paper proposes one such polymorphic network architecture. We demonstrate its modes of configurability, and evaluate the polymorphic network architecture design space, producing polymorphic fabrics that minimize the network area overhead. Finally, we expand the network on chip design space to include a polymorphic network design, showing that a single polymorphic network is capable of implementing all of the pareto optimal fixed-network designs.

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The network architecture of the Connection Machine CM-5 (extended abstract)

Cited by 220 publications

References 11 publications

A scalable, commodity data center network architecture

A scalable, commodity data center network architecture

Data Center Switch Architecture in the Age of Merchant Silicon

Polymorphic On-Chip Networks

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