The New DRAM Interfaces: SDRAM, RDRAM and Variants

Abstract

Abstract. For the past two decades, developments in DRAM technology, the primary technology for the main memory of computers, have been directed towards increasing density. As a result 256 M-bit memory chips are now commonplace, and we can expect to see systems shipping in volume with 1 G-bit memory chips within the next two years. Although densities of DRAMs have quadrupled every 3 years, access speed has improved much less dramatically. This is in contrast to developments in processor technology where speeds have doubled nearly every two years. The resulting "memory gap" has been widely commented on. The solution to this gap until recently has been to use caches. In the past several years, DRAM manufacturers have explored new DRAM structures that could help reduce this gap, and reduce the reliance on complex multilevel caches. The new structures have not changed the basic storage array that forms the core of a DRAM; the key changes are in the interfaces. This paper presents an overview of these new DRAM structures.

International Symposium on Computer Architecture (ISCA 2004)

“…DRAM vendors have recently announced numerous core variations that improve access time. For example, Enhanced Memory System's ESDRAM improves performance over regular SDRAM by adding an SRAM cache for the full row buffer, thereby allowing precharge to begin immediately after an access and DRAM writes to go directly to the core without destroying read locality [5,7,6]. Fujitsu's FCRAM subdivides each internal bank by activating only a portion of each word line, thereby reducing capacitance on the word access and improving access time over that of standard SDRAM to roughly 30ns [9,10].…”

“…Several vendors have placed large amounts of SRAM onto the DRAM die, in addition to the row buffers, in an attempt to reduce latency. For example, NEC'S VCDRAM places a set-associative SRAM buffer on the die that holds an implementation-defined number of sub-page (typically 10-100), where a sub-page is a subset of the bits activated by a column access and is on the order of 16-32 bytes [6,10].…”

“…The operation of the traditional DRAM was defined several decades ago, and as this has become a performance bottleneck, a number of evolutionary and revolutionary changes have been made [26]. The performance of many of these DRAMs in the context of a fixed bus architecture has been studied recently [5,7,6], and more detail on the nature of DRAM operation can be found there and elsewhere [26,18].…”

Concurrency, latency, or system overhead

“…DRAM vendors have recently announced numerous core variations that improve access time. For example, Enhanced Memory System's ESDRAM improves performance over regular SDRAM by adding an SRAM cache for the full row buffer, thereby allowing precharge to begin immediately after an access and DRAM writes to go directly to the core without destroying read locality [5,7,6]. Fujitsu's FCRAM subdivides each internal bank by activating only a portion of each word line, thereby reducing capacitance on the word access and improving access time over that of standard SDRAM to roughly 30ns [9,10].…”

High-Bandwidth Network Memory System Through Virtual Pipelines

“…The various types of DRAM differ primarily in their interfaces at the chip and bus level [26]- [28], but the idea of banking is always there. Experimental evidence [28] indicates that on average PC133 SDRAM works at 60% efficiency and DDR266 SDRAM works at 37% efficiency, where 80%-85% of the lost efficiency is due to the bank conflicts.…”