The New Small Wheel electronics

Abstract

The increase in luminosity, and consequent higher backgrounds, of the LHC upgrades require improved rejection of fake tracks in the forward region of the ATLAS Muon Spectrometer. The New Small Wheel upgrade of the Muon Spectrometer aims to reduce the large background of fake triggers from track segments that don't originate from the interaction point. The New Small Wheel employs two detector technologies, the resistive strip Micromegas detectors and the “small” Thin Gap Chambers, with a total of 2.45 million electrodes to be sensed. The two technologies require the design of a complex electronics system given that it consists of two different detector technologies and is required to provide both precision readout and a fast trigger. It will operate in a high background radiation region up to about 20 kHz/cm2 at the expected HL-LHC luminosity of ℒ = 7.5 × 1034 cm-2 s-1. The architecture of the system is strongly defined by the GBTx data aggregation ASIC, the newly-introduced FELIX data router and the software based data handler of the ATLAS detector. The electronics complex of this new detector was designed and developed in the last ten years and consists of multiple radiation tolerant Application Specific Integrated Circuits, multiple front-end boards, dense boards with FPGA's and purpose-built Trigger Processor boards within the ATCA standard. The New Small Wheel has been installed in 2021 and is undergoing integration within ATLAS for LHC Run 3. It should operate through the end of Run 4 (December 2032). In this manuscript, the overall design of the New Small Wheel electronics is presented.

Novel developments on the OpenIPMC project

“…Many of these boards are compliant with the PICMG Advanced Telecommunication Computing Architecture (ATCA) standard [2]. Examples of these boards are the Apollo [3], the Serenity [4], the ATLAS Trigger Processor [5] and the CMS DAQ and Timing Hub [6]. The ATCA standard requires all boards to be equipped with an Intelligent Platform Management Controller (IPMC), which monitors the health of the boards and manages their power state as part of the Hardware Platform Management (HPM) infrastructure.…”

The ATLAS experiment at the CERN Large Hadron Collider: a description of the detector configuration for Run 3

“…More detailed descriptions of the architecture, design considerations, and functionality of all the electronics described in this section are provided in ref. [85].…”

“…The FEBs are all described in detail in ref. [85]. The left-hand box of figure 61 illustrates the major similarities and differences between the three types of FEB.…”

“…This substantially reduces both the required bandwidth and the amount of centroid and track-finding logic. The board responsible for this decision-making is the sTGC Pad Trigger [85], located in the Rim Crate for each sector, and implemented in radiation-and magnetic field-tolerant electronics. Placing the boards at the rim of the wheel, where radiation is less intense, allows the flexibility of forming the pad tower coincidence in programmable logic on FPGAs.…”

“…sTGC Router. The sTGC Router [95] serves as a packet switch for routing strip charge information from the strip-TDS on the sFEBs to the sTGC Trigger Processor (TP) [85]. There is one per layer for each sector.…”