The Output Noise Reduction of the Multiplexer

Abstract

A new approach to reducing output noises of the multiplexer (MUX) is presented. In contrast to other methods, this one reduces the noise with a strength equal to the strength of the noise in specific cases. The method is based on adding logic cells and transistors in the circuit and choosing its sizes corresponding to the delay time of the output signal and to the strength of the output noise. In general, the main device that is used for reducing output noises in digital and analog circuits it’s capacitor. But in the circuits which scheme structure depends from its bit number, the output noise strength depends from the quantity of the switching inputs of the scheme. As high will be the switching inputs, as bigger will be the strength of the output noises. The same capacitor can keep the accuracy of the output signal in certain cases of switching inputs combinations. Here is developed a method, by which each combination of switching inputs turns on appropriate output elements by which the accuracy of the output signal is saved in any case. The method is very comfortable using in MUX, because its inputs mostly are symmetrical, and it helps to use the method adding the output elements with nearly same sizes. The symmetrical structure of the inputs of the MUX is useful for the method, also observing the input-output signal delay time. By using this method on 2-to-1 MUX designed in 32 nm technology, the area of the circuit increases by 28% and the noise error decreases by 59%.