The need for phase (timing) control in a digital network is described. Because of unknown and unstable path delays, phase control is done on a local basis, whereas only frequency control is feasible on a global basis. The means to provide frequency control is potentially built into the network as a hierarchical masterislave system. The characteristics of the four levels of quality of the frequency sources (clocks) in this system are described. Each clock must be phase-locked to a clock of equal or better quality (e.g., S-3 locked to S-2). The pull-in range of the phase-lock loop associated with a clock must allow for inaccuracies of the clock to which it locks-even under startup conditions. The pull-in range for an S-3 clock expressed on a fractional frequency basis is about 9 X The importance of this number is placed in perspective by realizing two things: 1) the goal for frequency accuracy of a signal controlling an S-3 clock is a minimum of 3.5 X 2) it is the current intention to equip about 98 percent of the 10 000 digital switches with S-3 clocks. This means that almost all S-3 clocks will be directly connected to an S-3, not an S-2, clock. Furthermore, many other types of equipment, such as digital cross connects and digital channel banks (based on S-3 or S-4 clocks), will intentionally or inadvertently become sources of timing signals. The magnitude of the potential problem therefore becomes apparent. Experience in the field indicates that the number of instances of synchronization problems today is troublesomely large. The three major causes of these problemsequipment and line failures, design errors, and operational errorsare discussed. Means of limiting these problems, including the greater use of high-quality equipment and better system monitoring, are also discussed.