The Pleiades Architecture

Abnous, A.; Zhang, Hui; Wan, M.; George, Varghese; Prabhu, V.; Rabaey, Jan M.

doi:10.1002/0470845902.ch17

Cited by 5 publications

(6 citation statements)

References 25 publications

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“…The Pleiades project [6] proposes an architecture template for ultralow-power high-performance reconfigurable computing. It includes a general purpose processor coupled with a heterogeneous array of autonomous applicationspecific satellite processors.…”

Section: Related Workmentioning

confidence: 99%

HoneyComb: An Application-Driven Online Adaptive Reconfigurable Hardware Architecture

Thomas

Rückauer

Becker

2012

International Journal of Reconfigurable Computing

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Since the introduction of the first reconfigurable devices in 1985 the field of reconfigurable computing developed a broad variety of architectures from fine-grained to coarse-grained types. However, the main disadvantages of the reconfigurable approaches, the costs in area, and power consumption, are still present. This contribution presents a solution for application-driven adaptation of our reconfigurable architecture at register transfer level (RTL) to reduce the resource requirements and power consumption while keeping the flexibility and performance for a predefined set of applications. Furthermore, implemented runtime adaptive features like online routing and configuration sequencing will be presented and discussed. A presentation of the prototype chip of this architecture designed in 90 nm standard cell technology manufactured by TSMC will conclude this contribution.

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Section: Related Workmentioning

confidence: 99%

HoneyComb: An Application-Driven Online Adaptive Reconfigurable Hardware Architecture

Thomas

Rückauer

Becker

2012

International Journal of Reconfigurable Computing

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“…The Pleiades architecture was proposed by the University of California at Berkeley targeting DSP algorithms [1]. In the Pleiades architecture (see figure 2.5), a control processor, usually a GPP, is surrounded by a heterogeneous array of satellite processors (SPs).…”

Section: Coarse-grained Reconfigurable Architecturesmentioning

confidence: 99%

“…The satellite processors can be optimized for specific algorithm domains such as computationally intensive DSP algorithms. An example of such satellite processor in [1] is a processor called Maia, which is six times more energy-efficient than the DSP solution for executing a speech coding algorithm. This idea is quite similar to the motivation of the Annabelle heterogenous MPSoC architecture.…”

Section: Coarse-grained Reconfigurable Architecturesmentioning

confidence: 99%

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Cognitive radio on a reconfigurable platform

Zhang¹

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Due to the explosive growth of wireless communication, the demands for radio spectrum are rapidly increasing. It is very difficult to accommodate new wireless services under the current spectrum allocation scheme. On the other hand, the allocated spectrum is not efficiently utilized. Cognitive Radio is proposed as a technology to solve the imbalance between spectrum scarcity and spectrum under-utilization. Spectrum utilization can be improved by making it possible for a user who does not have the license for spectrum (secondary user) to access the spectrum which is not occupied by the licensed user (primary user). This secondary user has the awareness of the spectrum and adapts its transmission accordingly on a non-interference basis. This spectrum access and awareness scheme is referred to as Cognitive Radio. The idea is also known as Dynamic Spectrum Access (DSA) or Open Spectrum Access (OSA). Cognitive Radio is seen as the final point of software defined radio (SDR) platform evolution. A fully flexible and efficient software defined radio platform will be the enabling technology for Cognitive Radio. Cognitive Radio imposes a number of requirements on the processing platform such as flexibility, energy efficiency and guaranteed throughput/latency. The trend in the implementation of SDR is moving towards Multiprocessor System-on-Chip (MPSoC) platforms.The work of this PhD thesis is part of the Ad-hoc Adaptive Freeband (AAF) project. The aim of the AAF project is to design a Cognitive Radio based wireless ad-hoc network for emergency situations. Although the AAF project addresses Cognitive Radio in a holistic fashion from physical layer to networking issues, the work of this thesis mainly focuses on the design of the adaptive physical layer (baseband processing). The physical layer considered in this thesis mainly consists of two parts: transmission and spectrum sensing. A reconfigurable MPSoC platform is used to support the adaptive baseband processing of Cognitive Radio. A coarse-grain reconfigurable processor called the Montium, developed at the University of Twente, is considered in this thesis as a key element of the proposed MPSoC platform. v The Montium targets the 16 bit Digital Signal Processing (DSP) algorithm domain. It offers a combination of flexibility and energy efficiency.Although MPSoCs offer many advantages, it is a challenging task to map applications onto MPSoCs, especially highly dynamic applications such as Cognitive Radio. There is a gap between the application models used for the specification of such applications and an optimized implementation of the application on an MPSoC. To close the gap, we propose to use a task transaction level (TTL) interface approach both for developing the Cognitive Radio application at system level and for the platform interface between the application and the proposed MPSoC platform. The TTL approach is used throughout the thesis as the system-level design methodology and its advantages are elaborated by mapping adaptive physical layer algorithms for...

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“…PADDI-2 presents a data-driven execution feature and improved processing elements built on an array that is still fine-grained and homogeneous 37 [65]. Finally, the Pleiades architecture, shown in figure 2.19, is a reusable architecture platform with a heterogeneous network of coarse-grained processing elements that can be programmed for a selected application domain [14]. Some EHW platforms are bio-inspired architectures, such as POEtic tissue, which contained three layers (phenotype, mapping, and genotype) to support three processes (evolution, development, and learning) [15], as shown in figure 2.20.…”

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confidence: 99%

Hexarray: A Novel Self-Reconfigurable Hardware System

Hussein¹

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The Pleiades Architecture

Cited by 5 publications

References 25 publications

HoneyComb: An Application-Driven Online Adaptive Reconfigurable Hardware Architecture

HoneyComb: An Application-Driven Online Adaptive Reconfigurable Hardware Architecture

Cognitive radio on a reconfigurable platform

Hexarray: A Novel Self-Reconfigurable Hardware System

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