The potential of the cell processor for scientific computing

Abstract

The slowing pace of commodity microprocessor performance improvements combined with ever-increasing chip power demands has become of utmost concern to computational scientists. As a result, the high performance computing community is examining alternative architectures that address the limitations of modern cache-based designs. In this work, we examine the potential of using the forthcoming STI Cell processor as a building block for future high-end computing systems. Our work contains several novel contributions. First, we introduce a performance model for Cell and apply it to several key scientific computing kernels: dense matrix multiply, sparse matrix vector multiply, stencil computations, and 1D/2D FFTs. The difficulty of programming Cell, which requires assembly level intrinsics for the best performance, makes this model useful as an initial step in algorithm design and evaluation. Next, we validate the accuracy of our model by comparing results against published hardware results, as well as our own implementations on the Cell full system simulator. Additionally, we compare Cell performance to benchmarks run on leading superscalar (AMD Opteron), VLIW (Intel Itanium2), and vector (Cray X1E) architectures. Our work also explores several different mappings of the kernels and demonstrates a simple and effective programming model for Cell's unique architecture. Finally, we propose modest microarchitectural modifications that could significantly increase the efficiency of double-precision calculations. Overall results demonstrate the tremendous potential of the Cell architecture for scientific computations in terms of both raw performance and power efficiency.

Acceleration of a 3D Euler Solver Using Commodity Graphics Hardware

“…For such sub-block sizes, the surface-to-volume ratio is low enough to get good data reuse. The overall approach is similar to that described by Williams [17] et al for structured grid applications on the Cell microprocessor.…”

Synchronization methods in parallel and distributed discrete-event simulation

“…Data sharing between the cores relies on software-managed DMA transfer that requires proper memory address alignment. Since its introduction, a wide variety of scientific and multimedia applications have been successfully ported to the Cell with significant performance improvements (see, e.g., [160]). In order to realize the Cell's potential in PDES applications, Liu and Wainer proposed a technique that adopts a data-flow oriented strategy to exploit data-and event-level parallelism in a simulation, combining multi-grained parallelism and different optimizations to accelerate both memory-bound and compute-bound computational kernels [161].…”

Accelerating Agent-Based Ecosystem Models Using the Cell Broadband Engine

“…The Cell Broadband Engine in particular has shown great promise for accelerating scientific applications due to its Stream Processing architecture [10] [11]. This paper investigates the use of the Cell Broadband Engine to accelerate a class of agent-based Virtual Ecology models for use in oceanographic research.…”