An optimal design procedure to achieve minimum power consumption for a given technology and gain bandwidth is presented. Regulated cascode gain enhancement is used to ensure sufficient DCgain at minimum gate length transistors. To validate the approach five folded cascode OTA's have been implemented, spanning a bias range of 1A -10mA, with measured unity-gain bandwidths within 20% of the designed value. For 17 mW at 3 V, a 0.5 m CMOS OTA achieves 630 MHz with 51 phase margin. The method has been applied in the design of a 3rd order modulator for GSM receivers. The modulator consumes 2.8 mW at 3 V and has a dynamic range of 86 dB for a 100 kHz input signal bandwidth.