The POWER8&lt;sup&gt;TM&lt;/sup&gt; processor: Designed for big data, analytics, and cloud environments

Friedrich, Joshua; Le, H. Q.; Starke, William J.; Stuechli, Jeff; Sinharoy, Balaram; Fluhr, Eric; Dreps, Daniel; Zyuban, Victor; Still, Gregory; González, Christopher; Hogenmiller, David; Malgioglio, F.; Nett, Ryan; Puri, Ruchir; Restle, P.J.; Shan, David; Deniz, Zeynep; Wendel, D.; Ziegler, Matt; Victor, Dave

doi:10.1109/icicdt.2014.6838618

Cited by 16 publications

(9 citation statements)

References 3 publications

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“…We believe that this idea can be generalized to other systems with separate request/response channels such as buffer-on-board memory systems [7] (e.g., Intel SMB [22], IBM Centaur [13], etc. ), the evaluation of which is left for our future work.…”

Section: Balanced Dispatch: Idea and Evaluationmentioning

confidence: 99%

PIM-enabled instructions

Ahn

Yoo

Mutlu

et al. 2015

Proceedings of the 42nd Annual International Symposium on Computer Architecture

331

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Processing-in-memory (PIM) is rapidly rising as a viable solution for the memory wall crisis, rebounding from its unsuccessful attempts in 1990s due to practicality concerns, which are alleviated with recent advances in 3D stacking technologies. However, it is still challenging to integrate the PIM architectures with existing systems in a seamless manner due to two common characteristics: unconventional programming models for in-memory computation units and lack of ability to utilize large on-chip caches.In this paper, we propose a new PIM architecture that (1) does not change the existing sequential programming models and (2) automatically decides whether to execute PIM operations in memory or processors depending on the locality of data. The key idea is to implement simple in-memory computation using compute-capable memory commands and use specialized instructions, which we call PIM-enabled instructions, to invoke in-memory computation. This allows PIM operations to be interoperable with existing programming models, cache coherence protocols, and virtual memory mechanisms with no modification. In addition, we introduce a simple hardware structure that monitors the locality of data accessed by a PIM-enabled instruction at runtime to adaptively execute the instruction at the host processor (instead of in memory) when the instruction can benefit from large on-chip caches. Consequently, our architecture provides the illusion that PIM operations are executed as if they were host processor instructions.We provide a case study of how ten emerging data-intensive workloads can benefit from our new PIM abstraction and its hardware implementation. Evaluations show that our architecture significantly improves system performance and, more importantly, combines the best parts of conventional and PIM architectures by adapting to data locality of applications.

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Section: Balanced Dispatch: Idea and Evaluationmentioning

confidence: 99%

PIM-enabled instructions

Ahn

Yoo

Mutlu

et al. 2015

Proceedings of the 42nd Annual International Symposium on Computer Architecture

331

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“…As digital processing technology has become more advanced and accessible, the parallel processing hardware of real-time simulators has improved in terms of the size and complexity of the networks that can be represented and the simulation timesteps that can be maintained in real time. The current generation (2017 to time of writing) of processing hardware for the RTDS Simulator is based on a multicore processor: IBM ® 's POWER8™, which has ten available cores [5]. The processor has been custom-integrated at the embedded level for the real-time application.…”

Section: Expanding the Tightly-coupled Network Solutionmentioning

confidence: 99%

Advancements in Real-Time Simulation for the Validation of Grid Modernization Technologies

Sidwall

Forsyth

2020

Energies

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Real-time simulation and hardware-in-the-loop testing have increased in popularity as grid modernization has become more widespread. As the power system has undergone an evolution in the types of generator and load deployed on the system, the penetration and capabilities of automation and monitoring systems, and the structure of the energy market, a corresponding evolution has taken place in the way we model and test power system behavior and equipment. Consequently, emerging requirements for real-time simulators are very high when it comes to simulation fidelity, interfacing options, and ease of use. Ongoing advancements from a processing hardware, graphical user interface, and power system modelling perspective have enabled utilities, manufacturers, educational and research institutions, and consultants to apply real-time simulation to grid modernization projects. This paper summarizes various recent advancements from a particular simulator manufacturer, RTDS Technologies Inc. Many of these advancements have been enabled by growth in the high-performance processing space and the emerging availability of high-end processors for embedded designs. Others have been initiated or supported by developer participation in power industry working groups and study committees.

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“…The 649 mm 2 POWER8 processor die includes twelve architecturally enhanced eight-way multithreaded cores with high-throughput private second-level caches, a 96-MB high-bandwidth eDRAM third-level cache, an on-chip symmetric multi-processor (SMP) fabric, a set of cryptography and memory compression accelerators, memory controllers with I/O links capable of connecting to a maximum of eight memory buffer chips [4], six high-bandwidth off-chip SMP links, and 32 third-generation PCI Express** (PCIe**) lanes. Figure 1 shows the die photograph of the POWER8 processor.…”

Section: Chip Overviewmentioning

confidence: 99%

IBM POWER8 circuit design and energy optimization

Zyuban

Friedrich

Dreps³

et al. 2015

IBM J. Res. & Dev.

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The IBM POWER8i processor is a 649-mm 2 , 4.2-billion transistor, high-frequency microprocessor fabricated in the IBM 22-nm silicon on insulator (SOI) technology with embedded dynamic random access memory (eDRAM) and 15 layers of metal. With its twelve architecturally enhanced, eight-way multithreaded cores, 96-MB high-bandwidth shared third-level cache, and increased on and off-chip bandwidth, the POWER8 processor delivers industry-leading performance. This paper describes the circuit techniques and design methodologies that were employed for implementing this chip and that allowed it to maintain the power dissipation at the level of its predecessor while delivering a threefold increase in per-socket performance. Among the innovative technologies employed by the processor are resonant clocking, on-chip per-core voltage regulation, and enhanced eDRAM arrays. Chip overviewThe IBM POWER8* processor [1,2] is the eighth generation of IBM Power Architecture* implemented in IBM's 22-nm embedded dynamic random access memory (eDRAM) silicon on insulator (SOI) technology [3]. The 649 mm 2 POWER8 processor die includes twelve architecturally enhanced eight-way multithreaded cores with high-throughput private second-level caches, a 96-MB high-bandwidth eDRAM third-level cache, an on-chip symmetric multi-processor (SMP) fabric, a set of cryptography and memory compression accelerators, memory controllers with I/O links capable of connecting to a maximum of eight memory buffer chips [4], six high-bandwidth off-chip SMP links, and 32 third-generation PCI Express** (PCIe**) lanes. Figure 1 shows the die photograph of the POWER8 processor. The processor cores are grouped into four quadrants. Each core has a private 512-KB level-2 (L2) cache with a read bandwidth of 64 bytes per cycle. The shared 96-MB level-3 (L3) cache is physically placed into the core quadrants. The on-chip SMP buses connecting the processor cores, memory controllers, accelerators, and I/O units are running through the horizontal stripe in the center of the chip, referred to as Fabric in Figure 1, and the vertical wiring channel in the middle. The on-node SMP buses, responsible for intra-node communication, are located along the top edge of the die, while the off-node SMP buses, responsible for inter-node communication, are located along the bottom edge together with the PCIe links. The memory links connecting the POWER8 processor to a maximum of eight memory buffer chips are located on the left and right side of the die. The accelerator units are located between the two core quadrants in the upper half of the processor die. The POWER8 processor contains approximately 4.2 billion transistors. Compared to its predecessor, the POWER7* processor [2, 5, 6], the POWER8 chip achieves a 50% improvement in single-thread performance, a two-fold increase in the per-core performance, and a three-fold increase in the chip throughput when measured at the same frequency [7]. In terms of the maximum core and SMP bus frequencies, the POWER8 processor achieves an incremental ...

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The POWER8<sup>TM</sup> processor: Designed for big data, analytics, and cloud environments

Cited by 16 publications

References 3 publications

PIM-enabled instructions

PIM-enabled instructions

Advancements in Real-Time Simulation for the Validation of Grid Modernization Technologies

IBM POWER8 circuit design and energy optimization

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