The real‐time debugging monitor for the bell system 1A processor

Abstract

Real‐time computer systems can be difficult to test when their timing characteristics influence the occurrence of problems. Because of this, tools for debugging real‐time systems must account for the interference that they produce in the system they are monitoring. The debugging monitor for the Bell System 1A processor is an example of just such a tool. This paper examines the 1A processor debugging monitor, focusing on the division of the monitor into three separate devices: a hardware monitor that allows autonomous debugging; a resident monitoring program that allows debugging with a minimal interference to normal timing; and a separate mini‐computer monitor that offers extended capability at the expense of unrestricted interference.