2012
DOI: 10.1017/s0956796812000214
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The Reduceron reconfigured and re-evaluated

Abstract: A new version of a special-purpose processor for running lazy functional programs is presented. This processor -the Reduceron -exploits parallel memories and dynamic analyses to increase evaluation speed, and is implemented using reconfigurable hardware. Compared to a more conventional functional language implementation targeting a standard RISC processor running on the same reconfigurable hardware, the Reduceron offers a significant improvement in run-time performance.

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Cited by 7 publications
(3 citation statements)
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References 18 publications
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“…York Lava. Naylor and Runciman [2012] use York Lava to describe their Reduceron graph-reduction processor, which runs on an FPGA. This is a revival of the idea of programming-language specific processors that avoid the von Neumann bottleneck of a single global store.…”
Section: Other Lavasmentioning
confidence: 99%
“…York Lava. Naylor and Runciman [2012] use York Lava to describe their Reduceron graph-reduction processor, which runs on an FPGA. This is a revival of the idea of programming-language specific processors that avoid the von Neumann bottleneck of a single global store.…”
Section: Other Lavasmentioning
confidence: 99%
“…It refers to the computer system throughput limitation due to the characteristic of bandwidth for incoming and outcoming data. [ 4,5 ] All these issues pose severe problems to the future of conventional computer development. As a result, the alternatives to von Neumann systems started to emerge.…”
Section: Introductionmentioning
confidence: 99%
“…Η κομψότητα της σημασιολογίας των συναρτησιακών γλωσσών έχει συνδυαστεί αρκετές φορές με τεχνικές υλοποίησης σε χαμηλό επίπεδο: έχουν υπάρξει αρκετές προσπάθειες υλοποίησης συναρτησιακών γλωσσών σε υλικό [10,24,32,37,68,100,106,111,139,189,192,202,251,261,263,296] ενώ ιδέες του συναρτησιακού προγραμματισμού έχουν ενσωματωθεί σε γλώσσες περιγραφής υλικού (hardware description languages) [187,195,211,256,258]. Επιπλέον, η διάδοση του επαναδιαμορφώσιμου υλικού (reconfigurable hardware), όπως τα FPGA, προσφέρει νέες επιλογές για τη μεταγλώττιση προγραμμάτων σε υλικό (hardware compilation), για γλώσσες υψηλού επιπέδου [90,109,162,247,257], και ειδικά για γλώσσες ροής δεδομένων [43,44,92,120,141,246,259,272,280,304].…”
Section: υλοποιήσεις για αρχιτεκτονικές ροής δεδομένωνunclassified