The Resistivity of Zinc Oxide Under Different Annealing Configurations and Its Impact on the Leakage Characteristics of Zinc Oxide Thin-Film Transistors

Abstract

Abstract-Sputtered zinc oxide (ZnO) without intentional doping was thermally annealed and the dependence of its resistivity on different sample configurations and heat-treatment conditions was studied. The ZnO was either exposed to the ambience or sealed with an impermeable cover during the annealing. The resistivity resulting from the sealed configuration was found to be lower. The possible origins of the charge carriers responsible for the conductivity were investigated, with the most plausible one studied in greater detail using photoluminescence. The leakage current in the OFF-state of a field-effect thin-film transistor is largely controlled by the residual conductivity of the channel region of the transistor. For a ZnO transistor, this region is typically undoped and subjected to a series of thermal processes under a variety of coverage configurations during the course of the fabrication of the transistor. The implied correlation between the aggregate thermal treatment and the characteristics of a transistor in its OFF-state was investigated and demonstrated.

A Comparative Study on the Effects of Annealing on the Characteristics of Zinc Oxide Thin-Film Transistors With Gate-Stacks of Different Gas-Permeability

“…For a TFT annealed in N 2 , a steep rise in the I off was observed beyond a transition temperature (T tr_I off ) of 450°C, as has been reported [4] previously. On the other hand, a low I off was consistently maintained for a TFT annealed in O 2 , even up to a high temperature of 600°C.…”

“…The ρ was observed to change with the cyclic change of the ambience (Fig. 3a) and has been attributed to the respective generation or annihilation of donor-like defects [4] when annealed in N 2 or O 2 . The temperature-dependence of ρ after 20-minute isochronal anneals in N 2 is shown in Figure 3b, exhibiting a transition to a low ρ at a characteristic temperature T tr_ρ .…”

“…The schematic cross-sections of a ZnO TFT with phosphorus-doped source and drain (S/D) regions [4] are shown in Figure 1. 100 nm thick ZnO was room-temperature sputtered on a Corning Inc. Eagle-2000 glass in a 13.56 MHz radio frequency magnetron sputtering machine with an ambience of 10% oxygen (O 2 ) and 90% argon (Ar).…”

“…For annealing beyond 400°C in O 2 , the hysteresis was completely eliminated for a TFT with a gas-permeable gate-stack. However, for annealing beyond 400°C in N 2 , the generation of defects in the ZnO channel [4] replenished the depleted dipoles -resulting in a subsequent increase in | V th |.…”

“…This is particularly true for a TFT based on a metal-oxide semiconductor, since its properties have been shown [4] to sensitively depend on the permeability of the cover layer during a heat-treatment. In practice, the channel region of a TFT is covered by one or a combination of a gatestack [3], [5] or a passivation layer [6].…”