The role of the interfacial layer in polysilicon emitter bipolar transistors

Eltoukhy, A.A.; Roulston, D.J.

doi:10.1109/t-ed.1982.21043

Cited by 87 publications

(12 citation statements)

References 22 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In polysilicon emitter bipolar junction transistors, the interfacial SiO x layer contributes to block the injection of minority carriers from the base region. Some studies have indicated that quantum-mechanical tunnelling across the interfacial SiO x layer is the mechanism behind the reduction of minority-carrier recombination and the conduction of the majority carriers [6,7]. Other studies have shown that the presence of the interfacial layer is essential to selectively allow the transport of one type of carriers and block the other type [13,15,25,26].…”

Section: Role Of the Interfacial Sio X Layermentioning

confidence: 99%

“…Subsequent studies on polysilicon emitter BJTs have elucidated the critical role of the interfacial silicon oxide layer, without which a direct deposition of polysilicon onto the mono-silicon leads to epitaxial growth and high recombination [4,6,7]. The interfacial oxide layer itself can be a source of recombination, but it can be suppressed thanks to a positive response to hydrogenation [4,8].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Phosphorus-diffused polysilicon contacts for solar cells

Yan

Cuevas

Bullock

et al. 2015

Solar Energy Materials and Solar Cells

160

View full text Add to dashboard Cite

Section: Role Of the Interfacial Sio X Layermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Phosphorus-diffused polysilicon contacts for solar cells

Yan

Cuevas

Bullock

et al. 2015

Solar Energy Materials and Solar Cells

160

View full text Add to dashboard Cite

“…According to (4), S n,eff determines the gradient of n p at r = r 1 (semispherical) or at x = −W p (planar). The thermal limit of S n,eff = 10 7 cm/s does not coincide with the approximation (12) and (13) for S n,eff → ∞. For the planar reference scenario [see Fig.…”

Section: Model Input Parametersmentioning

confidence: 95%

A Simple Model Describing the Symmetric <formula formulatype="inline"><tex Notation="TeX">$I\hbox{--}V$</tex></formula> Characteristics of <formula formulatype="inline"><tex Notation="TeX">$\hbox{p}$</tex></formula> Polycrystalline Si/ <formula formulatype="inline"><tex Notation="TeX">$\hbox{n}$</tex></formula> Monocrystalline Si, and <formula formulatype="inline"> <tex Notation="TeX">$\hbox{n}$</tex></formula>

Peibst

Römer

Hofmann

et al. 2014

IEEE J. Photovoltaics

View full text Add to dashboard Cite

We present an analytical model for the current transport in polycrystalline (poly)Si/interfacial oxide/monocrystalline (c)-Si base junctions, which consistently describes the symmetrical behavior of an n + poly-Si emitter/p c-Si base and p + poly-Si emitter/n c-Si base configuration. Our model is focused on a regime within which the current transport is possibly dominated by a flow through oxide pinholes rather than by tunneling. For an emitter region assumed to form underneath the interfacial oxide by diffusion of dopants from the poly-Si into the c-Si, we calculate the minority charge carrier distribution and the resistance implied for majority charge carriers. With reasonable parameters, our model simultaneously reproduces the experimentally observed low emitter saturation current densities and low junction resistances values. Our model provides a plausible explanation for the high current gain observed in p-n-p and n-p-n bipolar transistors featuring a poly-Si emitter. In principle, the obtained correlation between recombination current and series resistance is analogous to the situation in a base region of a solar cell with local rear contacts. Thus, a poly-Si/c-Si junction can be explained within the framework of a classical p-n junction picture for a passivated, locally contacted emitter.

show abstract

“…First, for device physicists, the transistor current conduction mechanism is affected by the presence or absence of an interface [3]. Current carriers must tunnel through any interfacial oxide present [4], [5]. This greatly enhances the transistor current gain, but, the emitter resistance is also increased [6].…”

Section: Introduction Ince Polysilicon Emitters Have Become a Featmentioning

confidence: 99%

Comparison of bipolar NPN polysilicon emitter interface formation at three different manufacturing sites

Doyle

Barrett

Lane

et al. 1992

IEEE Trans. Semicond. Manufact.

View full text Add to dashboard Cite

High performance polysilicon emitter bipolar transistors have been observed to have significant repeatability and manufacturing problems due to the inhomogeneous nature of the emitter and, particularly, the polysilicon-single crystal interface. For the first time, this paper examines the formation of polysilicon emitters at three different fabrication facilities, with a view to understanding critical manufacturing steps. This work demonstrates the effects of different interface procedures on the formation of the native oxide interfaces and how the transistor electrical properties are affected. The sensitivity of the interface break up, by rapid thermal annealing, to the initial interface thickness is quantified. Significantly, polysilicon emitter transistors from the three processes are compared, and it is found that the devices with recrystallized polysilicon behave as ideal single crystal transistors.

show abstract

The role of the interfacial layer in polysilicon emitter bipolar transistors

Cited by 87 publications

References 22 publications

Phosphorus-diffused polysilicon contacts for solar cells

Phosphorus-diffused polysilicon contacts for solar cells

Comparison of bipolar NPN polysilicon emitter interface formation at three different manufacturing sites

Contact Info

Product

Resources

About