Abstract:Phase-change probe memory using Ge 2 Sb 2 Te 5 has been considered as one of the promising candidates as next-generation data storage device due to its ultra-high density, low energy consumption, short access time and long retention time. In order to utmostly mimic the practical setup, and thus fully explore the potential of phase-change probe memory for 10 Tbit/in 2 target, some advanced modeling techniques that include threshold-switching, electrical contact resistance, thermal boundary resistance and crysta… Show more
“…More importantly, owing to the advantageous traits of applied pulses such as low magnitude and short width, the required write energy per bit was excitingly reduced to 0.02 pJ for a crystallization pulse of 3 V of 200 ns and 0.05 pJ for an amorphization pulse of 3.8 V of 200 ns, respectively. Furthermore, the contact resistance introduced at the tip-ITO capping interface is calculated to be ~8 kΩ with mechanical properties introduced in Table 1, which is much lower than the case of DLC capping [25] having a contact resistance of ~80 kΩ, and can be ignored when compared with the whole device resistance usually in the range of hundreds of kΩ. These encouraging findings undoubtedly reveal the ability of this optimized electrical probe memory with ITO capping and bottom layer to provide ultrahigh areal density within fJ energy consumption during hundreds of ns period, certainly making it more competitive than electrical probe memories with either DLC or TiN capping and bottom layers and other probe memories utilizing different active materials from phase-change media.10.1080/14686996.2018.1534072-F0011Figure 11.Temperature variation at point A as a function of the pulse time for (a) crystallization and (c) amorphization, and the temperature distribution at point A at the onset of the pulse plateau for (d) crystallization and (d) amorphization.…”
Electrical probe memory has received considerable attention during the last decade due to its prospective potential for the future mass storage device. However, the electrical probe device with conventional diamond-like carbon capping and bottom layers encounters with large interfacial contact resistance and difficulty to match the experimentally measured properties, while its analog with titanium nitride capping and bottom layers also faces serious heat dissipation through either probe and silicon substrate. Therefore, the feasibility of using indium tin oxide (ITO) media for the capping and bottom layers of the electrical probe device is investigated by tailoring the thickness and electrothermal properties of the ITO capping and bottom layers within experimentally established range and subsequently calculating the resultant temperature at several predefined points based on a previously developed three-dimensional model. To meet the required temperature and to fit the experimentally reported values, the thickness, electrical conductivity, and thermal conductivity of the ITO capping and bottom layers are found to be 5 nm, 103 Ω−1 m−1, 0.84 W m−1 K−1, and 200 nm, 1.25 × 106 Ω−1 m−1, 0.84 W m−1 K−1, respectively. The practicality of using this optimized device to achieve ultrahigh density, ultralow energy consumption, ultrafast switching speed, low interfacial contact resistance, and high thermal reliability has also been demonstrated.
“…More importantly, owing to the advantageous traits of applied pulses such as low magnitude and short width, the required write energy per bit was excitingly reduced to 0.02 pJ for a crystallization pulse of 3 V of 200 ns and 0.05 pJ for an amorphization pulse of 3.8 V of 200 ns, respectively. Furthermore, the contact resistance introduced at the tip-ITO capping interface is calculated to be ~8 kΩ with mechanical properties introduced in Table 1, which is much lower than the case of DLC capping [25] having a contact resistance of ~80 kΩ, and can be ignored when compared with the whole device resistance usually in the range of hundreds of kΩ. These encouraging findings undoubtedly reveal the ability of this optimized electrical probe memory with ITO capping and bottom layer to provide ultrahigh areal density within fJ energy consumption during hundreds of ns period, certainly making it more competitive than electrical probe memories with either DLC or TiN capping and bottom layers and other probe memories utilizing different active materials from phase-change media.10.1080/14686996.2018.1534072-F0011Figure 11.Temperature variation at point A as a function of the pulse time for (a) crystallization and (c) amorphization, and the temperature distribution at point A at the onset of the pulse plateau for (d) crystallization and (d) amorphization.…”
Electrical probe memory has received considerable attention during the last decade due to its prospective potential for the future mass storage device. However, the electrical probe device with conventional diamond-like carbon capping and bottom layers encounters with large interfacial contact resistance and difficulty to match the experimentally measured properties, while its analog with titanium nitride capping and bottom layers also faces serious heat dissipation through either probe and silicon substrate. Therefore, the feasibility of using indium tin oxide (ITO) media for the capping and bottom layers of the electrical probe device is investigated by tailoring the thickness and electrothermal properties of the ITO capping and bottom layers within experimentally established range and subsequently calculating the resultant temperature at several predefined points based on a previously developed three-dimensional model. To meet the required temperature and to fit the experimentally reported values, the thickness, electrical conductivity, and thermal conductivity of the ITO capping and bottom layers are found to be 5 nm, 103 Ω−1 m−1, 0.84 W m−1 K−1, and 200 nm, 1.25 × 106 Ω−1 m−1, 0.84 W m−1 K−1, respectively. The practicality of using this optimized device to achieve ultrahigh density, ultralow energy consumption, ultrafast switching speed, low interfacial contact resistance, and high thermal reliability has also been demonstrated.
“…Later Wright’s model was expanded to three dimensions (3D) by Wang et al [ 48 , 49 , 50 ], who also introduced more physically realistic material properties (e.g., the thermal conductivity of the DLC media) and some important electrical/thermal behaviors previously ignored by Wright (e.g., threshold switching and electrical/thermal boundary resistance) into the improved model. This resulted in a newly optimized architecture composed of a SiO 2 encapsulated probe and a media stack consisting of 2 nm DLC capping with an electrical conductivity of 50 Ω −1 ⋅m −1 and a thermal conductivity of 0.5 W⋅m −1 ⋅K −1 , a 10 nm GST layer, and a 40 nm TiN bottom with an electrical conductivity of 5 × 10 6 Ω −1 ⋅m −1 and thermal conductivity of 12 W⋅m −1 ⋅K −1 .…”
Section: Current Status Of Phase-change Electrical Probe Memorymentioning
Phase-change electrical probe memory has recently attained considerable attention owing to its profound potential for next-generation mass and archival storage devices. To encourage more talented researchers to enter this field and thereby advance this technology, this paper first introduces approaches to induce the phase transformation of chalcogenide alloy by probe tip, considered as the root of phase-change electrical probe memory. Subsequently the design rule of an optimized architecture of phase-change electrical probe memory is proposed based on a previously developed electrothermal and phase kinetic model, followed by a summary of the state-of-the-art phase-change electrical probe memory and an outlook for its future prospects.
“…Given the fact that threshold voltage is approximately equal to the product of layer thickness and threshold field, a thin GST is usually preferable so as to reduce the threshold voltage and thus the written power for a given low writing pulse. Therefore, an optimized design of the electrical probe memory device has been proposed by taking into account aforementioned factors as well as the underlying issues from practical fabrication process [ 109 ], as shown in Fig. 14 .…”
Section: Reviewmentioning
confidence: 99%
“…The thickness of GST layer is fixed to be 10 nm, which is the typical thickness for phase-change probe memory [ 89 , 96 ]. The write and readout performances of the designed probe memory was assessed by a previously developed electro-thermal model that is, however, supplemented with several advanced modeling techniques including threshold switching, electrical contact resistance at PtSi/DLC interface, and thermal boundary resistance (TBR) at the interfaces of DLC/GST and GST/TiN [ 109 ]. The crystallization process in this model is determined by simultaneously solving the Laplace equation, classical heat transfer equation, and the nucleation-growth equation [ 6 , 58 , 103 ].…”
The current world is in the age of big data where the total amount of global digital data is growing up at an incredible rate. This indeed necessitates a drastic enhancement on the capacity of conventional data storage devices that are, however, suffering from their respective physical drawbacks. Under this circumstance, it is essential to aggressively explore and develop alternative promising mass storage devices, leading to the presence of probe-based storage devices. In this paper, the physical principles and the current status of several different probe storage devices, including thermo-mechanical probe memory, magnetic probe memory, ferroelectric probe memory, and phase-change probe memory, are reviewed in details, as well as their respective merits and weakness. This paper provides an overview of the emerging probe memories potentially for next generation storage device so as to motivate the exploration of more innovative technologies to push forward the development of the probe storage devices.
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