The Sandbridge SB3011 Platform

Glossner, John; Iancu, Daniel; Moudgill, Mayan; Nacer, Gary; Jinturkar, Sanjay; Stanley, Stuart; Schulte, Michael

doi:10.1186/1687-3963-2007-056467

Cited by 21 publications

(18 citation statements)

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“…The SB3000 SDR platform [6,7] is designed to exploit parallelism inherent in emerging communication applications at different levels of granularity. It has four SandBlaster DSP cores and an ARM core.…”

Section: The Sandbridge Sandblaster 3000mentioning

confidence: 99%

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CORDIC instructions for LDPC decoding on SDR platforms

Senthilvelan

Iancu

et al. 2011

Analog Integr Circ Sig Process

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Wireless protocols strive to increase spectral efficiency and achieve high data throughput. Low-density parity-check (LDPC) codes are advanced forward error correction (FEC) codes that use iterative decoding techniques to achieve close to the Shannon capacity. Due to their superior performance, state-of-art wireless protocols, such as WiMAX and LTE Advanced, are adopting LDPC codes. LDPC codes come with the high cost of drastically increased computational effort for decoding. Among the proposed decoding algorithms, the belief propagation (BP) algorithm leads to a good approximation of an optimal decoder; however, it uses compute-intensive hyperbolic trigonometric functions. To reduce the computational complexity, typical LDPC decoder implementations use simplified algorithms, such as the min-sum algorithm, at the expense of reduced signal processing performance. Efficient and accurate methods to compute hyperbolic trigonometric functions can facilitate the use of the BP algorithm in real-time LDPC decoder implementations. This paper investigates hyperbolic COordinate Rotation DIgital Computer (CORDIC) instruction set architecture (ISA) extensions for software-defined radio (SDR) processors to compute the hyperbolic trigonometric functions for LDPC decoding efficiently. The CORDIC ISA extensions are evaluated on the low-power multi-threaded Sandbridge Sandblaster TM SB3000 platform. The computational performance, numerical accuracy, hardware estimates, power consumption estimates, and memory requirements with the CORDIC ISA extensions are compared to a baseline implementation without these extensions on the SB3000.

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Section: The Sandbridge Sandblaster 3000mentioning

confidence: 99%

“…When profiling the BP algorithm on the SB3000 platform [6,7], a state-of-the-art SDR processor, we observed that more than 32% of the computation time is spent performing hyperbolic tangent computations.…”

mentioning

confidence: 97%

CORDIC instructions for LDPC decoding on SDR platforms

Senthilvelan

Iancu

et al. 2011

Analog Integr Circ Sig Process

Self Cite

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“…Multi-core architectures like Picochip [6], Infineon's MuSIC [7] or Sandbridge's SB3011 platform [8] argue high computational performance and high flexibility. They are homogeneous or heterogeneous DSP-centered and accelerator-assisted MPSoCs.…”

Section: B Related Workmentioning

confidence: 99%

Heterogeneous vs homogeneous MPSoC approaches for a Mobile LTE modem

Jalier¹,

Lattard²,

Jerraya³

et al. 2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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Abstract-Applications like 4G baseband modem require single-chip implementation to meet the integration and power consumption requirements. These applications demand a high computing performance with real-time constraints, low-power consumption and low cost. With the rapid evolution of telecom standards and the increasing demand for multi-standard products, the need for flexible baseband solutions is growing. The concept of Multi-Processor System-on-Chip (MPSoC) is well adapted to enable hardware reuse between products and between multiple wireless standards in the same device. Heterogeneous architectures are well known solutions but they have limited flexibility.Based on the experience of two heterogeneous Software Defined Radio (SDR) telecom chipsets, this paper presents the homoGENEous Processor arraY (GENEPY) platform for 4G applications. This platform is built with Smart ModEm Processors (SMEP) interconnected with a Network-on-Chip. The SMEP, implemented in 65nm low-power CMOS, can perform 3.2 GMAC/s with 77 GBits/s internal bandwidth at 400MHz. Two implementations of homogeneous GENEPY are compared to a heterogeneous platform in terms of silicon area, performance and power consumption. Results show that a homogeneous approach can be more efficient and flexible than a heterogeneous approach in the context of 4G Mobile Terminals.

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“…In order to give an indication of what may be achieved with the different types of elements, Table III provides some examples of implementation results from various published work [79], [80], [86], [87].…”

Section: ) Processing Elements Concluding Commentsmentioning

confidence: 99%

“…Examples of units that have SIMD processing elements and that are targeted for low-power consuming units, are the NXP Embedded Vector Processor (EVP) [78], [79], the Sandbridge SB3011 [80] and the Icera Livanto [81]. An example university approach is the SODA architecture [67].…”

Section: ) Real-time Reconfigurable Unitsmentioning

confidence: 99%

Software Defined Radio: Challenges and Opportunities

Ulversøy

2010

IEEE Commun. Surv. Tutorials

277

111

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Abstract-Software Defined Radio (SDR) may provide flexible, upgradeable and longer lifetime radio equipment for the military and for civilian wireless communications infrastructure. SDR may also provide more flexible and possibly cheaper multistandard-terminals for end users. It is also important as a convenient base technology for the future context-sensitive, adaptive and learning radio units referred to as cognitive radios. SDR also poses many challenges, however, some of them causing SDR to evolve slower than otherwise anticipated. Transceiver development challenges include size, weight and power issues such as the required computing capacity, but also SW architectural challenges such as waveform application portability. SDR has demanding implications for regulators, security organizations and business developers.Index Terms-Software defined radio, radio communication equipment, software engineering.

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The Sandbridge SB3011 Platform

Cited by 21 publications

References 0 publications

CORDIC instructions for LDPC decoding on SDR platforms

CORDIC instructions for LDPC decoding on SDR platforms

Heterogeneous vs homogeneous MPSoC approaches for a Mobile LTE modem

Software Defined Radio: Challenges and Opportunities

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