The SecretBlaze: A Configurable and Cost-Effective Open-Source Soft-Core Processor

Barthe, Lyonel; Cargnini, Luís Vitório; Benoit, Pascal; Torres, Lionel

doi:10.1109/ipdps.2011.154

Cited by 34 publications

(20 citation statements)

References 2 publications

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“…The latter gives the possibility to restore a previous valid state of the processor, for instance in the case of an execution error (soft errors) or a power failure. Both techniques are validated on two 32-bit embedded processors: Amber [7] and Secretblaze [8]. The HDL codes of both processors were modified to implement the two aforementioned capabilities.…”

Section: Stt-mram For Low-power Applicationsmentioning

confidence: 99%

Embedded systems to high performance computing using STT-MRAM

Senni

Delobelle

Coi

et al. 2017

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2017

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Abstract-The scaling limits of CMOS have pushed many researchers to explore alternative technologies for beyond CMOS circuits. In addition to the increased device variability and process complexity led by the continuous decreasing size of CMOS transistors, heat dissipation effects limit the density and speed of current systems-on-chip. For beyond CMOS systems, the emerging memory technology STT-MRAM is seen as a promising alternative solution. This paper shows first how STT-MRAM can improve energy efficiency and reliability of future embedded systems. Then, a hybrid design exploration framework is presented to investigate the potential of STT-MRAM for high performance computing.

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Section: Stt-mram For Low-power Applicationsmentioning

confidence: 99%

Embedded systems to high performance computing using STT-MRAM

Senni

Delobelle

Coi

et al. 2017

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2017

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“…The proposed node architecture as shown in the right of figure 1 consists of: a) Core: The chosen core is the SecretBlaze [5], which is an open-source 32-bit RISC soft-core processor, based on the ISA of the Xilinx's MicroBlaze. It implements a classic Harvard architecture with a 5-stage pipeline.…”

Section: B Architecture Of a Nodementioning

confidence: 99%

A novel flexible 16-core MP-SoC architecture based on parallel skeletons for image processing applications

Boussadi¹,

Tixier²,

Landrault³

et al. 2014

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)

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For many image processing systems, the computing power required can not be provided by a single sequential processor, this is why many designers appeal to multiprocessor systems (parallelism). This article proposes an original flexible MP-SoC (Multi-Processors System on Chip) architecture for image processing applications. Developing processors network systems tailored to a particular application domain is critical and design-time consuming in order to achieve high-performance customized solutions. This paper introduces a 16-core MP-SoC ASIC with a software configuration. In particular, each tile of the network can configure its communication links depending on the most relevant overall parallelism scheme for a targeted application. Results are shown in term of power, area and timing performance for a 65 nm CMOS technology ASIC design. A case study (grey scale histogram analyzes) is presented to illustrate the proposed flexible MP-SoC design methodology and enables to focus on architecture exploration, instantiated scheme of parallelization and timing performance.

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“…The SecretBlaze CPU [15] is a configurable open-source RISC soft-core processor developed by our research group. It implements the MicroBlaze instruction set architecture with a five-stage pipeline.…”

Section: B Npu Components Descriptionmentioning

confidence: 99%

“…The development platform is based on a Virtex 5 LX 110T FPGA, using optional multiplier, divider, and barrel shifter instructions [15]. These instructions are present into the Integer Unit (IU) of the SecretBlaze instance.…”

Section: Open-scale Area Evaluationmentioning

confidence: 99%

Open-Scale: A Scalable, Open-Source NOC-based MPSoC for Design Space Exploration

Busseuil

Barthe

Almeida

et al. 2011

2011 International Conference on Reconfigurable Computing and FPGAs

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International audienceAs complexity of embedded system increases, configurable hardware is becoming more attractive because it provides a fast and efficient basis for design development. As a consequence, one of the most promising embedded architecture consists in the replication of Processing Elements (PEs)connected through a Network-on-Chip (NoC). Such architectures provide computation parallelism, scalability, and reduced design time thanks to reusability. This paper describes the development of a scalable, distributed memory, open-source NoC-based platform called Open-Scale and itsimplementation into FPGA devices. The main objective of this platform is to provide a complete framework for research development on NoC-based distributed memory MPSoCs

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The SecretBlaze: A Configurable and Cost-Effective Open-Source Soft-Core Processor

Cited by 34 publications

References 2 publications

Embedded systems to high performance computing using STT-MRAM

Embedded systems to high performance computing using STT-MRAM

A novel flexible 16-core MP-SoC architecture based on parallel skeletons for image processing applications

Open-Scale: A Scalable, Open-Source NOC-based MPSoC for Design Space Exploration

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