The state of the art in interconnect simulation

Sabelka, R.; Harlander, C.; Selberherr, S.

doi:10.1109/sispad.2000.871194

Cited by 6 publications

(3 citation statements)

References 57 publications

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“…The calculation of R, C, and L matrices of a multi-port, multi-conductor interconnect requires a numerical or field solver approach, which solves Maxwell's electromagnetic field equations, with initial and boundary conditions [8,9]. The choice of numerical techniques to solve the partial differential equations includes the finite difference method (FD), the finite element method (FE), and the boundary element method (BEM) etc [8,9].…”

Section: Interconnect Modelingmentioning

confidence: 99%

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Modeling and characterization of copper interconnects for SoC design

Arora

2003

International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.

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Interconnect (wiring) is central to nanometer system-on-a-chip (SoC) design. As such, accurate interconnect modeling and characterization are key to the design and verification of SoCs. Today copper (Cu) has become a mainstream material for on-chip interconnections. Unlike aluminum (Al) interconnects, Cu wire line width and thickness is a function of wire width and spacing, wire-pattern density, and topography. These new effects must be modeled accurately for designs to achieve first-time silicon success. In this paper we discusses the Cu process and its impact on modeling the interconnect parasitic elements -resistance (R), capacitance (C), and inductance (L). For a given process node, use of Cu reduces interconnect delay and power, but from a design prospective, the same effect is achieved by reducing wire length. Impact of the X-Architecture, which makes pervasive use of diagonal lines and has the promise of reducing wire length to an average of 20%, is also discussed. Finally, silicon validation of interconnect R,C, and L model using a test-chip approach is covered.

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Section: Interconnect Modelingmentioning

confidence: 99%

“…The choice of numerical techniques to solve the partial differential equations includes the finite difference method (FD), the finite element method (FE), and the boundary element method (BEM) etc [8,9]. Both public-domain and commercial tools are available that are based on all these methods [8].…”

Section: Interconnect Modelingmentioning

confidence: 99%

Modeling and characterization of copper interconnects for SoC design

Arora

2003

International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.

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“…9. The limiting step in the characterization is solving the Maxwell equation to get the numerical results, but here substantial progress has been made as well [18].…”

Section: The Parameterized 3d-modelingmentioning

confidence: 99%

Precise extraction of ultra deep submicron interconnect parasitics with parameterized 3D-modeling

Frerichs

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)

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-Manufacturing induced optimizations in the mask preparation step by layout post processing and fabrication inherent imperfections, like trapezoidal interconnect cross sections or variations of the dielectric interlayer thickness, lead to increased mismatches between the layout based timing and signal integrity characterizations and the corresponding Silicon-based behavior measurable after fabrication. Thus, to ensure timing closure between silicon and layout, DFM (Design For Manufacturability) related optimizations need to be taken care of when performing the parasitics extraction step. An example will be given where the mismatch between measurement and layout based extraction data can be demonstrated already for a 0.25µm technology. It will further be shown that the inclusion of simplified process features by applying parameterized 3D-modeling will render sufficiently accurate extraction results. The proposed methodology is in addition efficient enough to handle complex layouts. Thus for all practical purposes parameterized 3D-modeling closes the gap between TCAD tools delivering highest accuracy, but limited to relatively small structures, and more powerful, but insufficiently accurate, standard full chip, layout based extraction tools.

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On convergence and inherent oscillations within computational methods employing fictitious sources

Fikioris

Tsitsas

2015

Computers & Mathematics with Applications

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The state of the art in interconnect simulation

Cited by 6 publications

References 57 publications

Modeling and characterization of copper interconnects for SoC design

Modeling and characterization of copper interconnects for SoC design

Precise extraction of ultra deep submicron interconnect parasitics with parameterized 3D-modeling

On convergence and inherent oscillations within computational methods employing fictitious sources

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