The study on the shaping of electroplated copper pillar bumping

Han, Ying Han Ying; Li, Ming; Sun, Hongqi; Sun, Jianliang

doi:10.1109/icept.2011.6066842

Cited by 3 publications

(1 citation statement)

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“…11,12 Many research efforts have been reported such as changing additives in electroplating solution and reducing the current density to get good copper pillar performance. [13][14][15] However the plating efficiency is still limited with lower plating current density, especially for the higher copper pillar (height > 100 um) bumps.…”

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confidence: 99%

Method to Improve the Process Efficiency for Copper Pillar Electroplating

Luo

Xue

et al. 2015

J. Electrochem. Soc.

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With the progress of wafer level and chip scale packaging, copper pillar bump technology has been applied in advanced assembly due to the advantage of fine pitch capability, better electrical performance and lower power consumption. As one of the critical process of copper pillar bump technology, electroplating process is gaining more and more interests from the semiconductor packaging R&D community. In this work, two different electroplating processes, i.e. single-rate plating method and multi-rate plating method, have been studied. The impacts on bump height co-planarity, copper pillar profile and wafer stress are further evaluated. By applying multi-rate plating method, better copper pillar bump performance and higher electroplating efficiency can be both achieved.

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confidence: 99%