The TaPaSCo Open-Source Toolflow

Abstract

The integration of FPGA-based accelerators into a complete heterogeneous system is a challenging task faced by many researchers and engineers, especially now that FPGAs enjoy increasing popularity as implementation platforms for efficient, application-specific accelerators for domains such as signal processing, machine learning and intelligent storage. To lighten the burden of system integration from the developers of accelerators, the open-source TaPaSCo framework presented in this work provides an automated toolflow for the construction of heterogeneous many-core architectures from custom processing elements, and a simple, uniform programming interface to utilize spatially distributed, parallel computation on FPGAs. TaPaSCo aims to increase the scalability and portability of FPGA designs through automated design space exploration, greatly simplifying the scaling of hardware designs and facilitating iterative growth and portability across FPGA devices and families. This work describes TaPaSCo with its primary design abstractions and shows how TaPaSCo addresses portability and extensibility of FPGA hardware designs for systems-on-chip. A study of successful projects using TaPaSCo shows its versatility and can serve as inspiration and reference for future users, with more details on the usage of TaPaSCo presented in an in-depth case study and a short overview of the workflow.

AGILER: An Adaptive Heterogeneous Tile-Based Many-Core Architecture for RISC-V Processors

“…Therefore, Tapasco [23] has been proposed as an opensource framework to generate multi-/many-core SoCs with custom PEs. The framework allows seamless integration of any HLS-based accelerator within a scalable architecture by auto-generating required wrapping logic and interfaces for interconnection and communication within the architecture.…”

“…RV64 ISA is supported inside a general purpose tile as well as a compute tile for HLS-based accelerator. Similar to Tapasco platform [23], ESP also auto generates the required wrapping logic and interfaces to seamless integrate custom hardware accelerators into the accelerator tile. Also, several programming models are supported through bare metal or Linux operating system.…”