The Test Features of the Quad-Core AMD Opteron- Microprocessor

Wood, Timothy J.; Giles, G.; Kiszely, C.; Schuessler, Mark; Toneva, D.; Irby, J.; Mateja, Michael

doi:10.1109/test.2008.4700551

Cited by 12 publications

(7 citation statements)

References 14 publications

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“…Designers in industry and academia have long addressed the same challenge ([3]- [12], to name a few). The SSM's design originally involved a custom processor called Imagine, in development by another Stanford group.…”

Section: Designing For Bringupmentioning

confidence: 99%

Bringing up a chip on the cheap

Wachs

Shacham

Asgar

et al. 2012

IEEE Des. Test. Comput.

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Section: Designing For Bringupmentioning

confidence: 99%

Bringing up a chip on the cheap

Wachs

Shacham

Asgar

et al. 2012

IEEE Des. Test. Comput.

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“…A test access mechanism, which supports three test modes for multiple identical cores, the full-rate self-compare mode, the interleaved self-compare mode and inter-core compare mode, is described. The inter-core compare mode is adopted in the quad-core AMD microprocessor [10]. Although it is flexible and scalable, pattern transformation and issuing proper TAM instructions are complex, and the support for X-masking will cost extra test time.…”

Section: Data-synchronous-comparator (Dsc) For Identical Coresmentioning

confidence: 99%

“…Thus, redefinition and redesign of test logics of the coming 8-core and 16-core chips will be minimized. Though the large amount of identical elements in the chip gives a chance for test time and data volume reduction by applying the same test patterns and testing them concurrently [7,8,9,10], it makes the scan architecture more complex and limits the fault diagnosis property of the chip. Trade-off among the ease of implementation, fault diagnosis and test throughput should be carefully considered with identical cores comparing techniques.…”

Section: Introductionmentioning

confidence: 99%

A Scalable Scan Architecture for Godson-3 Multicore Microprocessor

Qi¹,

Liu²,

Li³

et al. 2009

2009 Asian Test Symposium

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This paper describes the scan test challenges and techniques used in the Godson-3 microprocessor, which is a scalable multicore processor based on the SMOC (Scalable Mesh of Crossbar) on-chip network and targets high-end applications. Advanced techniques are adopted to achieve the scalable, low-power and low-cost scan architecture at the challenge of limited I/O resources and large scale of transistors. To achieve a scalable and flexible test access, a highly elaborate TAM (Test Access Mechanism) is implemented with supporting multiple test instructions and test modes. Taking advantage of multiple cores embedding in the processor, scan partitions are employed to reduce test power and test time, and test compression with more than 10X compression ratio are utilized to decrease the scan chain length. To further decrease test time, a Data-Synchronous-Comparator (DSC) is proposed for comparing the scan responses of the identical cores.

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“…By loading complex commands, operations like scan shift, capture, and mask are executed within each core. It is scalable and more flexible, but the biggest problems are to prove it on silicon and to develop the corresponding software [13] . Though the large amount of identical cores in the multicore processor give a chance for test time and data volume reduction by testing identical cores concurrently, it makes the scan architecture more complex and limits the test diagnosis property of the chip.…”

Section: Introductionmentioning

confidence: 99%

Design for Testability Features of Godson-3 Multicore Microprocessor

Liu

et al. 2011

J. Comput. Sci. Technol.

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This paper describes the design for testability (DFT) challenges and techniques of Godson-3 microprocessor, which is a scalable multicore processor based on the scalable mesh of crossbar (SMOC) on-chip network and targets high-end applications. Advanced techniques are adopted to make the DFT design scalable and achieve low-power and low-cost test with limited IO resources. To achieve a scalable and flexible test access, a highly elaborate test access mechanism (TAM) is implemented to support multiple test instructions and test modes. Taking advantage of multiple identical cores embedding in the processor, scan partition and on-chip comparisons are employed to reduce test power and test time. Test compression technique is also utilized to decrease test time. To further reduce test power, clock controlling logics are designed with ability to turn off clocks of non-testing partitions. In addition, scan collars of CACHEs are designed to perform functional test with low-speed ATE for speed-binning purposes, which poses low complexity and has good correlation results.

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The Test Features of the Quad-Core AMD Opteron- Microprocessor

Cited by 12 publications

References 14 publications

Bringing up a chip on the cheap

Bringing up a chip on the cheap

A Scalable Scan Architecture for Godson-3 Multicore Microprocessor

Design for Testability Features of Godson-3 Multicore Microprocessor

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