The TRAMOS pixel as a photo-detection device: Design, architecture and building blocks

Abstract

The deep trapping gate device concept for charged particle detection was recently introduced in Saclay/IRFU. It is based on an n-MOS structure in which a buried gate, located below the n-channel, collects carriers which are generated by ionizing particles. They deposit their energy in a volume which extends in the bulk, below the buried gate. The nchannel device is based on holes in-buried gate localization. Source-drain current modulation occurs, measurable during readout. The buried gate (Deep Trapping Gate or DTG) contains deep level centers which can be introduced during process or may be made with a Quantum Well. The device can be scaled down providing a micron range resolution. The proof of principle for such a device was verified using 2D device and process simulations. Work under way focusses on the study of building blocks. In this contribution, the pixel proof of design, using existing fabrication techniques will be discussed first. The use of this pixel for photon imaging will be discussed. 1 Corresponding Author. Nicolas Fourches: Tel.: +33(0)164463616; fax: +33(0)164463616: nicolas.fourches@cea.fr TRAMOS pixel operation principle and background Introduction: general concept and backgroundIn 2010 the deep trapping gate device concept (or TRAMOS: TRApping MOS) for charged particle detection was introduced by Saclay/IRFU [1]. It is based on an n-MOS structure in which a buried gate is located below the n-channel. Particles that generate electron-hole pairs by depositing energy in the volume located below the channel can be detected in the following way. Generated holes drift towards the channel and become localized in the buried gate. The subsequent change in the buried gate charge state leads to a modulation of the source-drain current. This new buried gate contains localized deep level centers (Deep Trapping Gate or DTG) which can be introduced during process, or alternatively a SiGe quantum well (Valence Band Well) can be used. The buried gate is then effective in localizing charge carriers during an amount of time sufficiently long to ensure adequate pixel readout (Fig.1) The point to point resolution of such a device, reduced to one single transistor (1μm 2 ), follows the down-scaling rules of standard CMOS processes. This low area sets the resolution below 1 μm which is a significant improvement with respect to DEPFET [2] and CMOS pixels. The TRAMOS proof of principle was verified using (TCAD) 2D device and process simulations [3]. Because it is depleted during detection the TRAMOS is potentially harder with respect to bulk damage than previous CMOS pixels. The pixel proof of design, using existing fabrications technique will be presented here. The use of this pixel for photons detection and imaging both of low and high energy is also possible. These pixel-arrays are primarily intended to be used in the inner-detectors for vertex determination in high energy physics experiments. We will focus on the technological steps that are necessary to fabricate the elementary pixel. Technological optionsTher...

Novel Sensors for Particle Tracking: a Contribution to the Snowmass Community Planning Exercise of 2021

“…A pixel design has been proposed [25,26]. The necessary simulations have been made to assess the functionality of the proposed device.…”