The use of almost linear phase IIR filters in DFT modulated filter banks for communication systems

Cacqueray-Valmenier, Mathias de; Coskun, Adem; Kale, I.

doi:10.1109/spawc.2016.7536754

Cited by 5 publications

(3 citation statements)

References 13 publications

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“…De Cacqueray‐Valmenier et al 8 explained the use and performance of M ‐path polyphase Infinite Impulse Response (IIR) filters for channelization, conventionally where Finite Impulse Response (FIR) filters are preferred. This paper specifically focuses on the Discrete Fourier Transform (DFT) modulated filter banks, which are known to be an efficient choice for channelization in communication systems.…”

Section: Literature Studymentioning

confidence: 99%

FPGA implementation of fast digital FIR and IIR filters

Seshadri

Ramakrishnan²

2019

Concurrency and Computation

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Summary The demand for digital signal processing optimized solutions grows drastically in the modern years, especially in the field of communication and modern signal processing circuits. The finite impulse response (FIR) and an infinite impulse response (IIR) filters play a crucial role in the design of any complex signal processing system. This paper exemplifies the conventional moving average (MA) FIR filters, fast MA FIR filters using look‐ahead arithmetic, the conventional IIR filters using combination of integrator and comb sections (CIC) method, and the fast IIR filters using look‐ahead arithmetic in detail. Altera EP4CE115F29C7 field‐programmable gate array (FPGA) device using Quartus II 13.1 synthesis tool has been used to implement these filters. The performance metrics like the number of Logic Elements (LEs), the performance, and the power immoderation simulation results are compared with the normal and fast MA FIR and IIR filters, respectively. The first‐order IIR conventional filter has 153.4 MHz performance shown in simulation result, the same filter with look‐ahead level 1 has 189.79 MHz performance, and the fast filter with level 2 has 199.96 MHz performance. In addition, with the MA FIR filters, an 8‐tap MA FIR filter using CIC method has 166.09 MHz performance, the same filter using look‐ahead with level 1 has 167.22 MHz performance, and the same filter using look‐ahead with level 2 has 168.56 MHz performance. The proposed FIR and IIR filter is designed efficiently in terms of speed for the application of VLSI signal processing environment.

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Section: Literature Studymentioning

confidence: 99%

FPGA implementation of fast digital FIR and IIR filters

Seshadri

Ramakrishnan²

2019

Concurrency and Computation

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“…In the literature there are various channelisation methods such as the uniform DFT-based Filter Banks (FB) [1][2][3], nonuniform filter banks [4][5][6], Host Windowing [7][8] and Coefficient Decimation [9-10] methods. However, when the complexity and power budget are considered, none of these methods alone provide a solution to demultiplex the spectrum into such a high number of sub-channels.…”

Section: Setup and Design Detailmentioning

confidence: 99%

On Board Processor and Processing Strategies for Next Generation Reconfigurable Satellite Payloads

Cetinsel

Coskun

Kale

et al. 2019

2019 9th International Conference on Recent Advances in Space Technologies (RAST)

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Today, the increasing demand in higher data rates necessitates new methods as well as higher flexibility for satellite telecommunication payloads in order to address a variety of applications and customers. This paper presents one of these processing strategies that is applicable to today's processing satellite payloads aiming to meet those demands. For this purpose, a two-tier filter bank is designed as part of a digital onboard processor, which first divides the spectrum at the output of the ADC into a number of sub-bands extracting all the stacked channels in the digital domain. Following the analysis section of the first tier of operations, the extracted channels go under a secondary channelisation process to obtain much finer granularity of 31.25 kHz or 50 kHz depending on the communication standard used for data transmission. The implementation of the channeliser was delivered on a bit-true simulation model and the input and the output of the channelisers were compared and evaluated both in the time and frequency domains.

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“…Again, Yuan et al [7] have discussed a new approach of FIR filter design using high-accuracy non-scaled stochastic adder so that the design has improved computation accuracy with less hardware resources. Similarly, De Cacqueray-Valmenier et al [8] have explained polyphase realization of IIR filters for implementing in wireless communication systems. This paper specially focused on the Discrete Fourier Transform (DFT) filter banks which are implemented by IIR filters instead of FIR filters.…”

mentioning

confidence: 99%

High performance IIR filter implementation on FPGA

Datta

Dutta

2021

Journal of Electrical Systems and Inf Technol

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This paper presents an improved design of reconfigurable infinite impulse response (IIR) filter that can be widely used in real-time applications. The proposed IIR design is realized by parallel–pipeline-based finite impulse response (FIR) filter. The FIR filters have excellent characteristics such as high stability, linear phase response and fewer finite precision errors. Hence, FIR-based IIR design is more attractive and selective in signal processing. In addition, the other two modern techniques such as look-ahead and two-level pipeline IIR filter designs are also discussed. All the said designs have been described in hardware description language and tested on Xilinx Virtex-5 field programmable gate array board. The implementation results show that the proposed FIR-based IIR design yields better performance in terms of hardware utilization, higher operating speed and lower power consumption compared to conventional IIR filter.

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The use of almost linear phase IIR filters in DFT modulated filter banks for communication systems

Cited by 5 publications

References 13 publications

FPGA implementation of fast digital FIR and IIR filters

FPGA implementation of fast digital FIR and IIR filters

On Board Processor and Processing Strategies for Next Generation Reconfigurable Satellite Payloads

High performance IIR filter implementation on FPGA

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